Panasonic TH-103PF12E, Руководство по обслуживанию

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TH-103PF12E
62
11.4. Block (1 of 8) Diagram
AUDIO_R
T
AUDIO_R
DVI_CN_SDA
T
T
TMDS_RXC-
DVI_CN_SCL
TMDS_RX2-
AUDIO_L
T
TMDS_RX1-
AUDIO_L
TMDS_RX0-
+15V
5V_STB
PA3301
D3011
JK3302
+14V_LAN
+5V
JK3301
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q3301
D3025
5V_STB
+3.3V_LAN
+5V
+3.3V
3.3V_LAN
X3302
Q3305
Q3304
PLL
IC3312
+1.8V
FACTORY
TC2-
WC
L
G0-G7
VCC
DATA RECOVERY
TA2+
FOR
H4
TD1-
B23
IIC CLOCK2
B19
R0-R7
LVDS_TX0-
NRST
R
ODD_R0-R7
EVEN_R0-R7
TD2+
DVI_5V_DET
HDE
GND
H1
USE
TD1+
2
COMPONENT
VIDEO IN
B5
IC3307
RXD
OE2
A21
TC1-
G0-G7
A5
A26
A40
VOUT
TVLOAD_IIC
XTAL IN
A28
H3
XIN
N_FHD
TXD
A12
USE
Q3303
+1.8V
B
SDA2
SCL2
B9
JK3301
+3.3V
TMDS
DECODER
WR
IC3305
AND
N.C.
TMDS_G
RESET
A2
B38
SDA0
SCL0
WR
FACTORY
DVI I/F RECEIVER
Q3303
TB1+
IC3301
A7
H2
CLK7(27MHz)
DVI-D INTERFACE
NRST
O_CLK
+5V
+9V
FREQ1
CLOCK CONTROL
10BASE-T/
SYNCHRONIZATION
LVDS_TX2-
TXD
TA1 -TE1
USE
DDCC
B26
B0-B7
HPS
TE2+
FACTORY
FOR
X3301
+3.3V
CSDA/CSCL
B25
EEPROM
A14
B23
10MHz
5V<->3.3V
RXD_S3
IIC_IF
VCC
IC3314
TA1-
R0-R7
COMPONENT VIDEO/LAN TERMINAL
FACTORY
TB1-
LVDS_TX6-
B21
L
+5V
TA1+
VCC(+3.3V)
TCK1
VCC(+1.8V)
SCL
EEPROM
B0-B7
TE1-
IC3345
TC2+
L
B0-B7
B14
DATA
ASD
DCLK
L
ODD_G0-G7
L
LVDS CONVERTER
R1PWR5V
CKOUT
B27
G0-G7
SLOT_IIC
SLOT+9V
SDA/
SCL
IC3310
CLK4
VCC(+3.3V)
S2
EVEN_B0-B7
FACTORY
EPCS_DATA
EPCS_ASD
EPCD_DCLK
AUDIO OUT L
B12
IC3316
IIC CONTROL(SRQ)
(+1.2V)
+15V
LVDS_TX4-
LAN TERMINAL
A15
N.C.
FREQ0
HL
L
FOR
EVEN_G0-G7
HD/FHD DET
100BASE-TX
LVDS_TX9-
RXD0
TXD0
(+3.3V)
IC3304
TA2 -TE2
EEPROM
LATCH
TD2-
IIC DATA2
VCC
H1
GENX_CONTROL_IIC
TB2-
A22
VCC
CLK
B8
3.3V->5V
DVI_CN_SDA/SCL
SPI
FLASH
MEMORY
B24
B15
AUDIO OUT L
LAN
DATA
GENX MPU
B
DDCD
FACTORY
IC3320
A23
TMDS_D1-
B0-B7
TC1+
SPI
AUDIO IN
A21
Q3302
OSCXO
VCC
B37
MII_TXD
MII_RXD
L
STB+5V(S)
AUDIO OUT R
IICDATA3
A36
H,V,CK
MII_MDC
Q3302
LVDS_TX5-
LVDS_TX7-
FOR
IC3313
USE
IC3314
5V<->3.3V
A26
IC3315
FOR
TMDS_D2-
TXD_S3
IC3301
B25
RESET
IIC_CLOCK3
25MHZ
A38
EDID_WP
N.C.
AUDIO IN
SLOT
IIC
A34
IC3346
Y/G
H,V,CK
N.C.
JK3303
MII_TXD/
MII_RXD
TCK1-
+1.8V
LVDS_TX1-
PR/R
USE
N.C.
A22
EEPROM
CONTROL IIC
STB+5V
RESET
SDA/
SCL
IIC_DATA3
TMDS_C-
L
25MHZ
LVDS_TX3-
G0-G7
OSCXI
VCC
H6
SDA
UART
DVI_5V_DET
RESET
SDA/SCL
HPD
+3.3V
B21
L
LVDS_TXC-
TB2+
+3.3V
SLOT_IIC
IC3302
A10
A4
IC3303
IIC-
CONTROL
(SRQ)
SDA
VCC
A3
A28
LAN+14V
5V->3.3V
H3
STB+5V
TE1+
+9V
LAN CONTROL
NETWORK
CONTROLLER
IC3308
TMDS_G
PLUG DET
FPGA
JK3302
SLOT+9V
FOR
VCC
SCL
3
TE2-
CONFIG ROM
10/100
EtherMAC
w/FIFO
IC3303
VCC(+3.3V)
RESET
1
L
MII DATA
B40
TMDS RX0 -RX2
IC3342
A
RXD
IC3341
DS12
PB/B
N.C.
H,V,CLK
USE
A8
L
S1
B11
B2
SDA1
SCL1
RESET
R0-R7
TMDS_G
LVDS_TX8-
TMDS_G
TMDS_D0-
B6
DSCL1/DSA1
AUDIO OUT R
TCK1+
IC3319
ODD_B0-B7
+9V
A9
DVI_IIC
VCC
H4/H5
DVI IN
SLOT_IIC
B24
+1.2V
B3
IC3308
VCC(+3.3V)
4
R0-R7
TA2-
SDA/SCL
+5V
A19
A
L
RGB
OUTPUT
A13
+15V
VCC
IC3343
HSYNC,VSYNC,DOCK
B39
DS13
LAN+14V
SLOT+9V