Panasonic SJ-MJ70, Руководство по обслуживанию

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Pin
No.
Mark I/O
Division
Function
54 SMON3 O Monitor signal output
terminal (Not used, open)
55 SMON2 O Monitor signal output
terminal
56 SMON1 O Monitor signal output
terminal
57 SMON0 O Monitor signal output
terminal (Not used, open)
58 FSEQ O Not used, open
59 VP O CLV servo clock judgement
output terminal (Not used,
open)
60 FOK O Focus OK signal output
terminal
61 DEFECT O Defect signal output
teminal (Not used, open)
62 UCLK O 4.2336MHz/8.4672MHz
output terminal (Not used,
open)
63 VDD1 I Powe supply terminal
64 VSS — GND terminal
65 VDD2 I Power supply terminal
66 CL I CPU interface data clock
input terminal
67 CE I CPU interface chip enable
signal input terminal
68 DI I CPU interface data input
terminal
69 DO O CPU interface data output
terminal
70 WRQ O CPU interface interrupt
signal output terminal
71 INT
72 ADIPW0 I Wobble signal input
terminal
73 RCUT I Input terminal for test
(Connected to GND)
74 PCK O VCEC clock signal output
terminal
75 VCVDD I Power supply terminal for
VCEC
76 FR I Bias resistor terminal of
VCEC osillation frequency
(Connected to power
supply through resistor)
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