Panasonic SDR-H200P, Руководство по обслуживанию

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CH2 CH1 V4 V3 V2 V1 TEST3 VDD VSS TEST2 NC NC HCLR VD FI PBLK
VDD
FCK20
FCK0
NSEL1 TEST4
TVMD
NC
VDD VSS
NC NC
AD CLK1
TEST5
AD CLK2
NC
TEST6
SUB
VSS
VDD2
H2
H1
R
VSS
VDD2
VDD
DS 1G
DS 2G
DS 1R
DS 2R
DS 1B
AVDD
AVSS
SPSIG
SPBLK
PBLK
/VD
DVDD
ADCLK
DVSS
DRDVDD
BLKSH
BLKFB
CDSIN
D9
D8
D7
D6
D5
D4
D3
D2
D1
BLKC
BIAS
AVDD
AVSS
TEST IN
VRM VRT VRB DVDD DVSS CS SDATA SCK D0
VSS
DS 2B
CCD HD
NC
NC
CLR
TEST1
FCK2I
VSS
VDD
S CLK
S DATA
SCS
CPOB
CPDM
NC
NC
THD
INPUT
DATA
SERIAL
S/R
V TIMING
GEN.
HCLR
CDS
COMPENSATION
CIRCUIT
DC OFFSET
BIAS GENERATOR
TIMING GENERATOR
SERIAL INTERFACE
OUTPUT LATCH CIRCUIT
PGA
10 BIT
ADC
S/R
H TIMING
GEN.
H PULSE
1/2f
DECODER
PULSE
Hi-SPEED
DECODER
V PULSE
DECODER
CH PULSE
DECODER
PULSE
PROCESS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
19
20
21
22
23
24
25
26
27
9
8
7
6
5
4
3
2
1
28 29 30 31 32 33 34 35 36
18 17 16 15 14 13 12 11 10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2 3 4 5 6 7
VDD
GND
14 13 12 11 10 9 8
1
IC105 IC- DETAIL BLOCK DIAGRAM
IC107,IC108,IC109 IC- DETAIL BLOCK DIAGRAM IC102,IC104 IC- DETAIL BLOCK DIAGRAM
SDR-H200P/SDR-H200PC
IC105 IC-DETAIL BLOCK DIAGRAM
IC107,IC108,IC109 IC-DETAIL BLOCK DIAGRAM
IC102,IC104 IC-DETAIL BLOCK DIAGRAM
SDR-H200P / SDR-H200PC
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