PAN1026A Bluetooth Module
3 Reference Design
Design Guide Rev. 1.0
Page 11
3
Reference Design
3.1 USB Evaluation Kit Schematic
3.2 Placement Recommendations
Antenna Keep-Out Area
Do not place any ground plane under the red marked restricted antenna area
in any layer! This would be affecting the performance of the chip antenna in a
critical manner.
The following conditions must be met:
Keep this product away from heat. Heat is the major cause of decreasing the life of these
products.
Keep this product away from other high frequency circuits.
+
3
V
3
+
3
V
3
n.c./0
n.c./0
0
.5
+
5
V
0 Ohm/47p
0 Ohm/47p
1µ
4µ7
B3U-1000P
1
k
5
+
3
V
3
USB_A
BLM15BB121SN1
4µ7
+
5
V
1
0
n
F
100nF
FT232RQ
BLM15BB121SN1
1
0
0
n
F
4µ7
+
3
V
3
100nF
0
0
0
0
0
0
+
5
V
PAN1026
PAN1026
n.c./0
n.c./0
100nF
n.c.
+
3
V
3
G
re
e
n
2
7
0
100nF
SO2520-000032
+
3
V
3
100nF
0
+3V3
0/n.c.
1
0
k
/n
.c
.
G
re
e
n
270
+
3
V
3
-Supply-Part
EN
3
IN
1
NC
4
OUT
5
IC3
TPS76933
R3
R2
R
1
5
C4
C5
C12
C11
S1
R
1
0
DN
2
DP
3
G
N
D
@
1
G
N
D
@
2
USB_GND
4
USB_VCC
1
X2
G
N
D
@
3
G
N
D
@
4
L2
C13
C
3
C1
IC2
VCC
19
3V3OUT
16
USBDP
14
USBDM
15
OSCO
28
OSCI
27
GND
4
TXD
30
RXD
2
RTS#
32
CTS#
8
DTR#
31
DSR#
6
DCD#
7
RI#
3
CBUS0
22
CBUS1
21
CBUS2
10
CBUS3
11
CBUS4
9
VCCIO
1
RESET#
18
GND
24
GND
17
TEST
26
GND
20
L1
C
8
C2
C6
R5
R6
R7
R8
R11
R12
RF
D9
GPIO5/FSYNC
C7
GPIO4/PCMCLK
C6
GPIO3/PCMIN
D6
GPIO2/PCMOUT
E7
GPIO16/DIN
D2
GPIO17/CS0X
C1
GPIO18/CS1X
D1
GPIO10/BTA
B3
GPIO11/BTS
B2
GPIO12/WIA
C3
GPIO13/BTI
C2
EEPROMWP
F2
GPIO14/SCL
E2
GPIO15/SDA
E1
GPIO6/UARTTX
F7
GPIO7/UARTRX
E6
GPIO8/RTS
F8
GPIO0/URDY
D4
URDY
E4
USBDP
F3
USBDM
F4
RESET
A3
PAN1026_PORTS
GPIO9/CTS
F5
GPIO1
D3
SLEEPCLK
F6
CLKRRQ
E5
VCC
A6
VCC
A5
VCC_DVDDB
A4
GND
F12
GND
F11
GND
F9
GND
F1
GND
E9
GND
E8
GND
D8
GND
D7
GND
C9
GND
C8
GND
A12
GND
A11
GND
A9
GND
A7
GND
A1
N.C.
C5
N.C.
C4
N.C.
B9
N.C.
B8
N.C.
B7
N.C.
B6
N.C.
D5
N.C.
B5
N.C.
B4
N.C.
B1
N.C.
A8
N.C.
A2
VDDUSB
E3
R13
R1
C10
R4
L
E
D
R
1
4
C9
STANDBY
1
GND
2
VDD
4
OUTPUT
3
IC1
C7
R
9
R16
1
2
3
4
5
6
7
8
9 10
X1
R
1
7
L
E
D
1
R18
DP
DP
RESET
RESET
DN
DN
MOD_RX
MOD_RX
MOD_TX
MOD_TX
MOD_CTS
MOD_CTS
MOD_RTS
MOD_RTS
USBDP
USBDP
USBDM
USBDM
GPIO0
GPIO0
SCL
SDA
SLEEPCLK
SLEEPCLK
GPIO1
GPIO1
GPIO13
GPIO13
GPIO12
GPIO12
GPIO11
GPIO11
GPIO10
GPIO10
GPIO18
GPIO18
GPIO17
GPIO17
GPIO16
GPIO16
GPIO5
GPIO5
Additional testpins
V1.2
Placement Difference for C4, C5, R1, R2, R3, R13 and R16:
due to different functions: UART or Direct USB
UART / Direct USB // The different variants are seperated by backslash. Left side is for UART, right side is USB direct.
This area will not be placed when USB is used
32.768kHz optional Oscillator
only needed when special sleep mode
USB is NOT supported yet by the IC
UARTAREA
PAN1026ETU Reference Design with UART and USB Option
DS-DG-1026ETU-205
IC1 is mounted on the board
Active mode
UFL
GND
