13.18. CAMERA SCHEMATIC DIAGRAM
A
1
B
C
D
E
F
G
2
3
4
5
6
15V
-7V
TO MAIN CN(E-7)
<TO CCD>
C6
C7
OUT
C8
C13
SUB
H2
C16
H1
C15
C14
R
V1
C9
C10
V2
V3
C11
C12
V4
12
LEVEL
CONVERTER
LEVEL
CONVERTER
LEVEL
CONVERTER
DRIVER
LEVEL
CONVERTER
LEVEL
CONVERTER
LEVEL
CONVERTER
LEVEL
CONVERTER
DRIVER
IC205
MN31121SA
V1
CH1
V2
ISUB
NC
VHH
VM24
V4
V3
GND
VH
SUB
VL
V2
VM13
VDC
V1
V3
V4
CH2
10
9
8
7
6
5
4
3
1
2
20
19
18
17
16
15
14
13
11
(CCD V DRIVE)
24
25
IC201
MN52A4
26
27
28
29
30
31
32
33
34
35
36
37
TEST3
SUBSW
VSS
VDD2
H2
VSS
VDD2
H1
R
VSS
VDD2
VDD1
PAL/NTS
TEST4
(CG/H DRIVE)
C203
16V10
C204
16V10
D202
RB520530
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
28
29
30
31
32
33
34
35
36
D201
MA2J11100L
C229
0.1
C202
35V1
C205
1000P
R210
1M
R204
3300
R203
3300
R202
3300
R213
0
R212
0
C217
1
C216
0.01
R206
33K
C213
1
C215
1
C212
1
C209
0.1
R209
0
C218
0.01
C219
6V10
R214
0
C214
4.7
CAM CS
CAM AFDR DTO
CAM AFDR CLK
ADINO
ADIN1
ADIN2
ADIN3
ADIN4
ADIN5
ADIN6
ADIN7
ADIN8
ADIN9
SERIAL
INTERFACE
BIAS
GENERATOR
DC OFFSET
COMPENSATION
CIRCUIT
TIMING
GENERATOR
CDS
PGA
10BIT
ADC
OUTPUT LATCH CIRCUIT
D1
D2
D3
D4
D5
D6
D7
D8
D9
ADCIN
AVSS
AVDD
BIAS
BLKC
CDSIN
BLKFB
BLKSH
AVDD
AVSS
DS2
DS1
CPOB
PBLK
DVDD
ADCLK
DVSS
DRDVDD
VRM
VRT
VRB
DVDD
DVSS
CS
SDATA
SCK
DO
IC202
C1AB00001725
(CDS/AGC/AD)
C220
0.1
CL209
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1
A2
A3
C201
0.1
C206
0.01
C208
6V10
B1
B2
B3
REFER TO MAIN CONNECTION
(MAIN C B A.)
12.0
-7.1
-7.1
12.0
2.6
2.7
2.6
-7.6
-7.6
-0.3
-0.3
3.3
0.1
2.7
0.1
2.7
1.4
2.0
0.9
2 7
2.8
0
2.8
1.3
1.4
1.3
1.3
1.3
1.6
1.0
0.6
0.3
0.1
0
1.3
2 7
0
0.7
0.7
2.7
1.9
1.9
1.9
1.9
1.2
2.7
3.3
1.6
3.3
1.6
0.3
3.3
2.7
0
2
NOTE:
THE MEA
DIAGRAM
0
60