Panasonic KX-HCM280, Руководство по обслуживанию

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Pin
No.
Pin Name I/O Description
53~60 Y[7~0] O Data Output B[7]:MSB, B[0]:LSB
ITU-RBT.656 Output Mode time: YCbCr 8 bit Data Output
8 bit (YCbCr) Output Mode time: YCbCr 8 bit Data Output
16 bit (YCbCr) Output Mode time: Y 8 bit Data Output
24 bit RGB Output Mode time: G 8 bit Data Output
61 DVDD - Digital part Power Supply
62 DGND - Digital part Ground
63~70 C[7~0] O Output Mode is set on the 27-28 pin or Register MRA[7:6]
71 ODD/EVEN O Field Indication Output
Odd Number Field time, "H" Output
72 HVALID O Horizontal effectual pixel timing Output
Effectual section time, "H" Output
73 VVALID O Vertical effectual pixel timing Output
Effectual section time, "H" Output
74 VSYNC_L O Vertical synchronizing signal (V sink) Output
75 HSYNC_L O Horizontal synchronizing signal (H sink) Output
76 CLKXO O Pixel Clock Output
Double speed Input Mode time (42 pin "0"):
Half frequency of System Clock Output
Normal speed Input Mode time (42 pin "0"):
Equal frequency of System Clock Output
77 CLKX2O O System Clock Output
System Clock Input is output direct.
78 DGND - Digital part Ground
79 DVDD - Digital part Power Supply
80 CLKX2O I System Clock Input (Select by Operation Mode)
Normal speed Input
Mode Double speed Input
Mode
NTSC ITU-RBT.601 13.5MHz 27MHz
NTSC Square Pixel 12.272727MHz 24.545454MHz
NTSC 4 Fsc setting is
possible only register setting
is MRA[3:1]. 14.31818MHz 28.63636MHz
PAL ITU-RBT.601 13.5MHz 27MHz
PAL Square Pixel 14.75MHz 29.5MHz
81 STATUS[3] O Status Signal Output
Select by Internal Register OMR[0]
OMR[1]: 0 FIFO Over flow detection Output
0: No detection/1: detection
OMR[1]: 1 CSYNC Output
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