S-6
S3.3. Camera Block Diagram
MOS IMAGE
SENSOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PS6011
G SIG 2 B
GND
GND
H2 B
SIGRS B
PW -1V
PW -1V
SHT
ALLRST
SCLK
SDATA
PW 5V
PW 5V
PW 5V
GND
G SIG 2 R
GND
H2 R
CS R
GND
CS G
H2 G
GND
GND
G SIG 2 G
G SIG 1 G
GND
H1 G
SIGRS G
GND
SIGRS R
H1 R
GND
G SIG 1R
GND
PW 2.9V
PW 2.9V
PW 2.9V
RSTN
V2
V1
VST
PW 2V
PW 2V
PW 3.3V
PW 3.3V
CS B
H1 B
GND
G SIG 1 B
IC301
(CAMERA DSP)
R1IN2
R1IN11
To IC703
(LENS DRIVE)
Y1OUT7
Y1OUT0
To IC3400
BUS37 DTY7
BUS37 DTY0
BUS37 STYC7
BUS37 STYC0
BUS37 DTC7
BUS37 DTC0
CK74
CLK27 CAM
CLK74 CAM
To IC3400
(VIDEO)
Y2OUT7
Y2OUT0
COUT7
COUT0
(VIDEO)
STORM VD
STORM LVD
STORM VD
STORM LVD
CK27 3V
CKL LENS 27M
STORM LHD
STORM HD
STORM LHD
STORM HD
7
CDS
PGA
SERIAL
I/F
10bit
ADC
29
30
31
D0
SCK
SD
AT
A
CS
D9
8
BLKFB
CDSIN
43
BLKC
9
BLKSH
DC OFFSET
COMPENSATION
CIRCUIT
BIAS
GENERATOR
6
BIAS
35 63 33
OUTPUT
LA
TCH
CIRCUIT
10bit
27
17
ADCLK
VR
T
VRM
VRB
13
12
SPBLK
SPSIG
TIMING
GENERATOR
14
OBP
CDS
PGA
SERIAL
I/F
10bit
ADC
58
59
60
SCK
SD
AT
A
CS
BLKFB
CDSIN
BLKC
BLKSH
DC OFFSET
COMPENSATION
CIRCUIT
BIAS
GENERATOR
2
BIAS
34 36 32
OUTPUT
LA
TCH
CIRCUIT
10bit
50
ADCLK
VR
T
VRM
VRB
46
45
SPBLK
SPSIG
TIMING
GENERATOR
47
OBP
26
56
25
55
24
23
22
52
75
D0
D9
81
80
57
79
78
54
77
53
76
74
3
4
39
5
AJ21
AH21
AG21
AF21
AJ22
AH22
AG22
AF22
AJ24
AH24
R2IN2
R2IN11
AG27
AF27
AG28
AG29
AF28
AF29
AE26
AE27
AE28
AE29
G1IN2
G1IN11
AD28
AD29
AC25
AC26
AC27
AB25
AB26
AB27
AB28
AB29
G2IN2
G2IN11
AA27
AA28
AA29
Y25
Y26
Y27
Y28
Y29
V25
V26
B1IN2
B1IN11
V29
U25
U26
U27
U28
U29
T25
T26
T27
T28
B2IN2
B2IN11
R26
R27
P29
P28
P27
P26
N29
N28
N27
N26
IC101-
Bch
(CDS/PGA&10bit ADC: R)
IC101-
Ach
(CDS/PGA&10bit ADC: R)
7
CDS
PGA
SERIAL
I/F
10bit
ADC
29
30
31
D0
SCK
SD
AT
A
CS
D9
8
BLKFB
CDSIN
43
BLKC
9
BLKSH
DC OFFSET
COMPENSATION
CIRCUIT
BIAS
GENERATOR
6
BIAS
35 63 33
OUTPUT
LA
TCH
CIRCUIT
10bit
27
17
ADCLK
VR
T
VRM
VRB
13
12
SPBLK
SPSIG
TIMING
GENERATOR
14
OBP
CDS
PGA
SERIAL
I/F
10bit
ADC
58
59
60
SCK
CS
BLKFB
CDSIN
BLKC
BLKSH
DC OFFSET
COMPENSATION
CIRCUIT
BIAS
GENERATOR
2
BIAS
34 36 32
OUTPUT
LA
TCH
CIRCUIT
10bit
50
ADCLK
VR
T
VRM
VRB
46
45
SPBLK
SPSIG
TIMING
GENERATOR
47
OBP
26
56
25
55
24
23
22
52
75
D0
D9
81
80
57
79
78
54
77
53
76
74
3
4
39
5
IC102-
Bch
(CDS/PGA&10bit ADC: G)
IC102-
Ach
(CDS/PGA&10bit ADC: G)
7
CDS
PGA
SERIAL
I/F
10bit
ADC
29
30
31
D0
SCK
CS
D9
8
BLKFB
CDSIN
43
BLKC
9
BLKSH
DC OFFSET
COMPENSATION
CIRCUIT
BIAS
GENERATOR
6
BIAS
35 63 33
OUTPUT
LA
TCH
CIRCUIT
10bit
27
17
ADCLK
VR
T
VRM
VRB
13
12
SPBLK
SPSIG
TIMING
GENERATOR
14
OBP
CDS
PGA
SERIAL
I/F
10bit
ADC
58
59
60
SCK
SD
AT
A
CS
BLKFB
CDSIN
BLKC
BLKSH
DC OFFSET
COMPENSATION
CIRCUIT
BIAS
GENERATOR
2
BIAS
34 36 32
OUTPUT
LA
TCH
CIRCUIT
10bit
50
ADCLK
VR
T
VRM
VRB
46
45
SPBLK
SPSIG
TIMING
GENERATOR
47
OBP
26
56
25
55
24
23
22
52
75
D0
D9
81
80
57
79
78
54
77
53
76
74
3
4
39
5
IC106-
Bch
(CDS/PGA&10bit ADC: B)
IC106-
Ach
(CDS/PGA&10bit ADC: B)
DS2R1
AJ16
DS1R1
AG15
ADCLKG
AH14
CSAFE1
AJ25
SDTATAAFE
AH26
DS2G1
AH16
DS1G1
AH15
CSAFE2
AF24
SCLKAFE
AJ26
CPOB
AF14
DS2B1
AG16
DS1B1
AJ15
CSAFE3
AG24
PW MOS -1V
5
1
4
3
2
IC103
PW 5V
5
1
4
3
2
IC107
PW 3R2V
5
1
4
3
2
IC105
PW 3R2V
5
1
4
3
2
IC104
PW 5V
MOSSENSOR ON
(IC2006-79)
AF8
AF7
AJ8
AH8
AG8
AJ9
AH9
AG9
AF9
AE9
AE11
AJ11
AJ12
AH11
AH12
AG11
IC301
(CAMERA DSP)
SDATA
SCLK
CSB
CSG
CSR
SIGRSB
SIGRSG
SIGRSR
ALLRST
RSTN
SHT
H2B
H1B
H2G
H1G
H2R
H1R
VST
V2
V1
AG12
AF11
AF12
AE12
J27
J26
F1
J28
J29
D9
E9
C8
D8
E8
C7
D7
E7
D12
E12
A11
B11
C11
D11
E11
C9
A5
B5
C5
D5
A4
B4
C4
D4
A15
A7
CK27 1R8V
X301
(Japan/P/PC/PL: 74.175MHz)
(Other areas
: 74.250MHz)
XIN148M H1
HDC-SD100 CAMERA CIRCUIT BLOCK DIAGRAM
SD
AT
A
SD
AT
A
Содержание HDCSD100P - HD VIDEO CAMERA
Страница 10: ...10 4 Specifications...
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