Panasonic FP2 Series, Руководство пользователя

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Confirming the Unit Settings and Design Contents FP2 Serial Data Unit
3 − 7
3.2 Setting the Transmission Speed and Transmission Format
Contents of the transmission format in the shared memory
Transmission format setting item Bit setting of shared memory
15 to 11 (
*
2) 10 9 8 7 6 5 4 3 2 1 0
Transmission speed 19200bps 0 0 1
9600bps 0 1 0
4800bps 0 1 1
2400bps 1 0 0
1200bps 1 0 1
600bps 1 1 0
300bps 1 1 1
Data length 7 bits 0
8 bits 1
Parity check Invalid 0 0
Odd parity 0 1
Even parity 1 1
Stop bit length 1 bit 0
2 bits 1
Control signals CS
and CD
Invalid 0
and CD
Valid 1
End code Any code ( * 1) 0 0
C
R
(H0D) 0 1
C
R
(H0D) and LF (H0A) 1 0
ETX (H03) 1 1
Start code Invalid 0
STX (H02)
Valid 1
Notes
1) The desired end code (any code) should be registered in
addresses 1001 (COM.1) and 1002 (COM.2) of the shared
memory. For information on the shared memory, see section
7.2.
2) Bit position 11 to 15 of addresses 1003 (COM.1) and 1004
(COM.2) must always be set to “0”.