Paia 9720, Инструкция по сборке и использованию

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26 9720 VCO 010321
as a voltage follower and used to charge C12 though R22 and the panel control R205. The
voltage on the capacitor is read out by a second voltage follower (IC7:D) and the follower
output voltage summed into total control voltage for OscA through R14 and OscB through the
normalization of J5 and R40.
Modulator - To follow the operation of the Modulator as ASR, imagine the Cycle switch S1 is
open. A high level at the Gate Input (J9) turns on Q5 so that the voltage at it's collector falls to
near ground. A couple of things happen in response to this - Q4 is turned on by the current
through R34 and its collector current begins to charge the timing capacitor C22 through the
Attack control R91. Also when Q5's collector voltage falls it turns off Q6 and Q6's collector
voltage goes high so that the current flow through R38 will hold Q5 on even if the Gate signal
goes away. The bistable action of Q6 and Q5 holds the modulator in the attack state until the
voltage on the timing cap reaches the peak voltage. IC8:D is a buffer that reads the voltage on
the timing cap C22. The output of the buffer drives LED1 through current limiting resistor R104
and also connects to the Output Level control R202.
IC8:C is configured as a comparator with hysteresis set by R101 which couples to the buffered
timing capacitor voltage and the positive feedback resistor network R100/R106. These values
are chosen so that when the timing voltage reaches 10V the voltage at the "+" input of the
comparator (pin 10) exceeds the reference voltage at the "-" input (pin 9) set by R96 and R103
and the comparator changes state with it's output going from -12V to about +10V. This voltage,
coupled though R102 turns on Q6 which causes it's collector voltage to go to ground. At this
point, if the Gate In is still true nothing further happens and the output Sustains at the peak
output level. If the Gate is off, or when it subsequently goes off, Q5 turns off and its collector
voltage goes high turning off Q4. With Q4 off the Decay part of the cycle is active and the
voltage on the timing capacitor decreasing as charge drains off through R33 and the Decay
control R201. Steering Diodes D1 and D2 force C22 to charge through R91 and discharge
through R201. R32 and C13 form a network that resets the comparator when an active Gate
causes Q4's collector to switch high.
When the timing voltage falls to about 1V the comparator's "+" input becomes less than the
"-" reference input and it's output falls from +10V to -12V, ready for the next Gate. When the
cycle switch (S1) is closed, this negative transition is coupled by R67 and C22 to the base of
Q6 and unconditionally turns this transistor off. Q6's now high collector voltage turns Q5, and
consequently Q4, on - starting the Attack cycle again.