LMX SERIES™ OPERATION MANUAL
SECTION 8:
Entire Contents Copyright
2018 by Pacific Power Source, Inc. (PPS) • All Rights Reserved • No reproduction without written authorization from PPS.
LMX Series Power Source Operation Manual
Page 368 of 463
8.12.3
SCPI Status Registers
The STATus:OPERation and STATus:QUEStionable registers provide information about the
present mode of operation.
•
Transition of a CONDition bit to the true state causes the EVENt bit to be set true.
•
Unmasked ENABle bits allow an EVENt bit to be reported in the summary bit for that
EVENt register in the STATUS BYTE register.
•
Setting an ENABLe bit true, unmasks the corresponding EVENt bit.
•
Reading an EVENt register clears it.
•
All :STATUS registers are 16 bits (Figure 5.3).
The STATus:OPERation register provides information about the present mode of operation.
Relevant commands for the STATus:OPERation register are:
:STATus:OPERation:CONDition?
:STATus:OPERation:ENABle
:STATus:OPERation:ENABle?
:STATus:OPERation:EVENt?
The STATUS:QUESTIONABLE register provides information about errors and questionable
measurements.
Relevant commands for the STATUS:QUESTIONABLE register are:
:STATus:QUEStionable:CONDition?
:STATus:QUEStionable:ENABle
:STATus:QUEStionable:ENABle?
:STATus:QUEStionable:EVENt?
Refer to Figure 8-4, “SCPI Status Registers Model” for details on registers.
