Onkyo TX-SR804, Руководство по обслуживанию

Страница: 98 / 237

LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
PDN
Modulator
AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS
VCOM
De-emphasis
Control
P/S
µP
Interface
Clock
Divider
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
Modulator
8X
Interpolator
DZFR
DZFL
SCF
LPF
ATT
ATT
1
MCLK
LRCK
BICK
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
Top
View
2
3
4
5
6
7
8
DZFL
DZFR
VSS
VDD
VCOM
AOUTL
AOUTR
P/S
16
15
14
13
12
11
10
9
PDN
SDTI
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power -Down Mode Pin
When at “ L” , the AK4384 is i n the power-down mode and is held in reset.
The AK4384 should always be reset upon power- up.
SMUTE I Soft Mute Pin in parallel mode
“ H” : Enable, “L” : Disable
6
CSN I Chip Select Pin in serial mode
ACKS I Auto Setting Mode Pin in parallel mode
“ L” : Manual Setting Mode, “ H” : Auto Setting Mode
7
CCLK I Control Data Clock Pin in serial mode
DIF0 I Audio Data Interface Format Pin in parallel mode 8
CDTI I Control Data Input Pin in serial mode
9 P/S I Parallel/Serial Select Pin
(Internal pull-up pin)
“ L” : Serial control mode, “ H” : Parallel control mode
10 AOUTR O Rch Analog Output Pin
11 AOUTL O Lch Analog Output Pin
12 VCOM O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1mF ceramic capacitor in parallel with
a 10 m F electrolytic cap.
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 DZFR O Rch Data Zero Input Detect Pin
16 DZFL O Lch Data Zero Input Detect Pin
BLOCK DIAGRAM
TERMINAL DESCRIPTION
PIN CONFIGURATION
Q2002: AK4384ET (192kHz 24-Bit 2ch DAC )
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -4
TX-SR804/804E