Onkyo TA-RW255 - Dual Cassette Deck, Руководство по обслуживанию, Страница: 99 / 106

TA-RW255
MICROPROCESSOR BLOCK DIAGRAM/ TERMINAL DESCRIPTION-2
Q701 MPD78042FGF-141
NO. PIN NAME SIGN DESCRIPTION
1 P94/FIP6 CAP MOTOR(A) O Capstan motor control output signal pin. (Deck-A)
2 P93/FIP5 CAP X1/~X2(A) O Capstan motor speed control output pin. (Deck-A)
3 P92/FIP4 SOLENOID(A) O Solenoid coil control signal output pin. (Deck-A)
4 P91/FIP3 1G O Grid (G1) control output pin.
5 P90/FIP2 2G O Grid (G2) control output pin.
6 P81/FIP1 3G O Grid (G3) control output pin.
7 P80/FIP0 4G O Grid (G4) control output pin.
8 VDD +5V I +5 V. Power supply pin.
9 P27/SCK0 DOLBY CLK O Clock control output pin of dolby IC.
10 P26/SO0/SB1 DOLBY DATA O Data control output pin of dolby IC.
11 P25/SI0/SB0 DOLBY STB O Strobe control output pin of dolby IC.
12 P24/BUSY ~DOLBY RST O Reset control output pin of dolby IC.
13 P23/STB 70/~120(A) O Play equalizer signal select output pin. (Deck-A)
14 P22/SCK1 70/~120(B) O Play equalizer signal select output pin. (Deck-B)
15 P21/SO1 PB X1/~X2 O Playback frequency bandwidth select signal output pin.
16 P20/SI1 LINE MUTE O Line mute signal control output pin.
17 RESET ~RESET I Reset signal input pin.
18 P74 REC MUTE(B) O Recording mute signal control output pin. (Deck-B)
19 P73 ~POFF I power stoppage detection input pin.
20 AVSS GND I GND. For A/D port of power supply.
21 P17/ANI7 ~FT MODE I Test mode setting input pin. For factory.
22 P16/ANI6 ~TEST MODE I Mechanism test mode input pin.
23 P15/ANI5 SIGNAL LCH I Display the level of L-channel/ search signal of A/D input pin.
24 P14/ANI4 SIGNAL RCH I Display the level of R-channel/ search signal of A/D input pin.
25 P13/ANI3 VOLUME I VOLUME A/D input pin.
26 P12/ANI2 KEY(2) I Key A/D input pin.
27 P11/ANI1 KEY(1) I Key A/D input pin.
28 P10/ANI0 KEY(0) I Key A/D input pin.
29 AVDD +5V I 5V. Power supply.
30 AVREF +5V I Power supply pin for A/D port.
31 P04/XT1 I Not used. To connect to GND.
32 XT2 Not used. Open pin.
33 VSS GND I GND pin.
34 X1 X1 I Clock signal input pin. (5MHz)
35 X2 X2 O Clock signal output pin.
36 P37 BIAS(B) O Bias control output signal pin. (Deck-B)
37 P36/BUZ NORMAL BIAS(B) O Bias (Normal) control output signal pin. (Deck-B)
38 P35/PCL HIGH BIAS(B) O Bias (High) control output signal pin. (Deck-B)
39 P34/TI2 REC/~PB(B) O R/P head select output signal pin. (Deck-B)
40 P33/TI1 DECK ~A/B O R/P head select output signal pin. (Deck-A/B)
41 P32/TO2 R.SENS(B) I Detect the reel rotation input signal pin. (Deck-B)
42 P31/TO1 R.SENS(A) I Detect the reel rotation input signal pin. (Deck-A)
43 P30/TO0 CAP MOTOR(B) O Capstan motor control signal output pin. (Deck-B)
44 P03/INTP3/C CAP X1/~X2(B) O Speed control of capstan motor output pin.
45 P02/INTP2 SOLENOID(B) O Solenoid control output pin. (Deck-B)
46 P01/INTP1 ~RI OUTPUT O RI signal output pin.
47 P00/INTP0/T RI_INPUT I RI signal input pin.
48 IC(VPP) GND I GND. Internal connection pin.
49 P72 ~PACK SW(A) I Tape installation detection input signal pin. (Deck-A.)
50 P71 HIGH SW(A) I Ta e class (HIGH) detection si nal in ut terminal. (Deck-A)
I/O
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