HA12167FB/HA12169FB
20
Under 5.3 V
Within –0.2 V
0
Figure 2 Input Level
Serial Data Formatting
14 bit shift register is employed.
CLK and data are stored during STB being high and data is latched when STB goes high to low.
Reset goes reset a state when reset low and high releasles reset. (High fixed at use time)
Attention Point of Serial Interface
•
Reset goes low condition when a power supply is ON or OFF.
•
Characteristics select of Bias DAC is connected with equalizer tape selector.
•
Bias DAC register is all low when a time of tape select.
•
Bias DAC register is all low and Bias DAC out is dropped low level at compulsion by force.
•
Input pin select, REC/PB select and Input volume gain select does not select at the same time.
•
Input volume must go mute condition when selected of RPI is input pin select.
CLK
2
3
4
5
6
7
8
9
10
11
12
13
Latch of data
Figure 3 Serial Data Timming Chart Figure
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