TX-SR402/8240/HT-R420
COMPRESSED
DATA INPUT
INTERFACE
DIGITAL
AUDIO
INPUT
INTERFACE
PLL
CLOCK MANAGER
FRAMER
SHIFTER
INPUT
BUFFER
CONTROLLER
RAM INPUT
BUFFER
PARALLEL or SERIAL HOST INTERFACE
24-BIT
DSP PROCESSING
RAM
PROGRAM
MEMORY
ROM
PROGRAM
MEMORY
RAM
DATA
MEMORY
ROM
DATA
MEMORY
STC
RAM
OUTPUT
BUFFER
OUTPUT
FORMATTER
RESET
DATA7:0,
EMAD7:0,
GPIO7:0
CS
RD,
R/W,
EMOE,
GPIO11
WR,
DS,
EMWR,
GPIO10
SCDIO,
SCDOUT,
PSEL,
GPIO9
A0,
SCCLK
A1,
SCDIN
ABOOT,
INTREQ
EXTMEM,
GPIO8
DD
DC
MCLK
SCLK
LRCLK
AUDATA[2.0]
XMT958/AUDATA3
FILT2
FILT1
VA
AGND
DGND(3:1)
VD(3:1)
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
6
5
4
3
2
1
A1,SCDIN
RD,R/W,EMOE,GPIO11
WR,DS,EMWR,GPIO10
AUDATA3,XMT958
DGND1
VD1
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
AUDATA2
DC
DD
RESET
AGND
VA
FILT1
FILT2
CLKSEL
CLKIN
CMPREQ,LRCLKN2
CS
SCDIO,SCDOUT,PSEL,GPIO9
INTREQ,ABOOT
EXTMEM,GPIO8
SDATAN1
VD3
DGND3
SCLKN1,STCCLK2
LRCLKN1
CMPDAT,SDATAN2,RCV958
CMPCLK,SCLKN2
A0,SCCLK
DATA7,EMAD7,GPIO7
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
VD2
DGND2
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
PIN LAYOUT
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-4
Q701:CS493264(DSP IC)-1
BLOCK DIAGRAM
