EVBUM2565/D
www.onsemi.com
5
Power Supply
The Evaluation and Development Board can be powered
by one of the following:
•
Micro USB port with regulator
•
External power supply connector (
P5
) with regulator
•
External power supply connector (
P5
) without
regulator
Use the jumpers on pin headers
P4
,
P7
and
P10
to select
a power supply option as show in Table 1.
Table 1. POWER SUPPLY SELECTION
Power Source
Jumper Position on P4
Jumper Position on P7
Jumper Position on P10
Micro USB Port with Regulator
1&2
2&3
1&2
External Power Supply with Regulator
3&4
2&3
1&2
External Power Supply without Regulator
5&6
2&3
2&3
Table 2. MINIMUM/MAXIMUM EXTERNAL REGULATED VOLTAGES
Power Supply
Header
Input Voltage
Minimum
Typical
Maximum
RSL10 SIP and J
−
Link OB MCU
EXT
−
PSU Regulated
3.3 V
3.6 V
12.0 V
RSL10 SIP and J
−
Link OB MCU
USB
−
5.0 V
−
RSL10 SIP
EXT
−
PSU Unregulated
1.1 V
1.25 V
3.6 V
Level Translators
The board has level translators for the DIO signals of the
RSL10 SIP, including the clock signal. The level translators
facilitate interfacing to external devices that operate at
a higher voltage than the RSL10 SIP.
VDDO and 3.3 V are two different power rails. The
translator allows a logic signal on the VDDO side to be
translated to either a higher or a lower logic signal voltage
on the 3.3 V side, and vice-versa.
The level translation circuitry consists of components
U4
and the
2x4
header. Signals are translated from the
VDDO
voltage reference to 3.3 V (default) voltage provided by the
regulator output or by an external supply. The VDDO
voltage is configured by the pin on header
P11
(located on
the board edge) to either
VBAT_DUT
, 3.3 V or other level
within the VDDO voltage range, which is 1.1 to 3.3 V.
The NLSX5014 level translators are bi-directional. They
have the following features:
•
Wide voltage operating range: 0.9 V to 4.5 V
•
VDDO and 3.3 V are independent
•
VDDO can be equal to, or less than, 3.3 V when
connected to the power rail
To enable the level translators, populate positions R34 and
R35 with 0 ohms. By default, the level translators are
disabled. NOTE: Enabling the level translator affects power
consumption.
LED Circuitry
There are two LEDs on the board. One is a dual color LED,
called LD1, connected to the J
−
Link emulator
microcontroller unit (MCU). The other is the green LED,
connected to DIO 6 of RSL10 SIP. You can use this LED
within your applications as an indication LED by
programming DIO 6. If DIO 6 is high, this LED is on.
Measuring the Current Consumption
This section deals with measuring current consumption
for the Evaluation and Development Board.
Headers are provided for each of the regulated voltages
for additional capacitance and/or for measurements. RSL10
SIP has 16 digital I/Os. The VDDO pin in header P9
configures the I/O voltages for power domains to VBAT.
The VBAT pin in header P10 configures the VBAT source.
The power select pin in header P4 configures the power
source of the RSL10 SIP. In addition the measurements
should be done by connecting an ammeter to current
measure header P3 to measure the device power
consumption in isolation.
To measure the current consumption of RSL10 SIP only,
you need to source the chip using the external power supply
without the regulator as shown in Table 2. To remove
leakage currents during current measurement, remove the
jumpers on header SWD. Removing the jumpers between
the MCU and the RSL10 SIP that connect nRESET, SWDIO
and SWCLK prevents current leakage from the JTAG
interface, avoiding inaccurate current measurements. In
addition, DIOs 4, 5 and 6 must be configured to High
−
Z
(disabled) with no pull up in software. DIOs 4 and 5 are
directly connected to the Atmel chip and will leak power into
it. DIO 6 is directly connected to the transistor driving the
LED and can leak power into it.
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