NCV7425EVB
http://onsemi.com
2
Figure 1. NCV7425EVB
NCV7425
1
V
CC
V
BB
2
3
4
5
6
7
10
11
12
13
14
15
16
LIN
GND
GND
WAKE
INH
OTP_SUP
RxD
TxD
RSTN
STB
EN
TEST
SOIC
−
16 LEAD
WIDE BODY
EXPOSED PAD
CASE 751AG
NCV7425 PIN CONNECTIONS
8
9
N.C.
N.C.
Getting Started
Master/Slave Configuration
The NCV7425 evaluation board can be configured as
Master or Slave node. Furthermore, Master node LIN bus
pull-up resistance (R
LIN
) can be tied to VBB supply line or
to INH pin (See the figures below).
The EMC immunity of the Master-node device can be
further enhanced by adding a capacitor between the LIN
output and ground (C
LIN
). The optimum value of this
capacitor is determined by the length and capacitance of the
LIN bus, the number and capacitance of Slave devices, the
pull-up resistance of all devices (Master and Slave), and the
required time constant of the system.
VBB
LIN Bus
NCV7425
VBB
INH
LIN
R
LIN
C
LIN
VBB
LIN Bus
NCV7425
VBB
INH
LIN
R
LIN
C
LIN
VBB
LIN Bus
NCV7425
VBB
INH
LIN
C
LIN
Figure 2. Master with Pull-up to VBB
Figure 3. Master with Pull-up to INH
Figure 4. Slave Configuration
Basic Connection
A simple LIN network configuration is shown in the
figure below. One Master and one Slave node is required
(Master/Slave Configuration).
MASTER Node
VBAT
SLAVE Node
LIN
GND
MCU
GND
VCC
MASTER
MCU
GND
VCC
SLAVE
Figure 5. NCV7425 Evaluation Setup Connection
