NCN5192NGEVB
http://onsemi.com
8
The interface towards a microcontroller is provided in
IDC
1
. This interface can also be used to supply power to the
module. The nominal supply voltage for the module is 3 V.
For more information see the section on power supply and
references.
The RESETB line to the modem is an open drain signal.
A pull-up resistor of 200 k
W
is provided on the board, and
should not be duplicated on the microcontroller side. The
reset signal is generated on the board, and could be used as
reset signal for other IC such as the microcontroller.
The CD signal rises when a HART signal of ca. 100 mVpp
is detected on the current loop. See the section on reference
voltages for more information on these threshold level
settings. When no signal, or a signal of limited amplitude is
present, the CD line is pulled down to 0 V.
The RxD, TxD, and RTSB signals implement a standard
UART interface at 1200 baud with start bit, 8 data bits, parity
bit and stop bit (11-bit frame). The RTSB signal disconnects
the transmitter circuit when pulled high, and should be held
low before any data is transmitted. Data frames are not
buffered by the modem. Instead, data is transmitted bit by
bit. Care should be taken to avoid clock skew in the receiving
UART. If the same time base is used for both the modem and
the UART, a 1% accurate time base may not be sufficient.
The problem is a combination of receive data jitter and clock
skew between transmitting and receiving HART devices. If
the transmit time base is at 99% of nominal and the receive
time base in another device is at 101% of nominal, the
receive data (at the receiving UART) will be skewed by
roughly 21% of one bit time at the end of each 11-bit byte.
This is shown in Figure 10. The skew time is measured from
the initial falling edge of the start bit to the center of the 11th
bit cell. This 21% skew by itself is a relatively good result.
However, there is another error source for bit boundary jitter.
The Phase Lock Loop demodulator in the NCN5192
produces jitter in the receive data that can be as large as 12%
of a bit time. Therefore, a bit boundary can be shifted by as
much as 24% of a bit time relative to its ideal location based
on the start-bit transition. (The start-bit transition and a later
transition can be shifted in opposite directions for a total of
24%).
The clock skew and jitter added together is 45%, which is
the amount that a bit boundary could be shifted from its
expected position. UARTs that sample at mid-bit will not be
affected. However, there are UARTs that take multiple
samples during each bit to try to improve on error
performance. These UARTs may not be satisfactory,
depending on how close the samples are to each other, and
how samples are interpreted. A UART that takes a majority
vote of 3 samples is acceptable.
Even if your own time base is perfect, you still must plan
on a possible 35% shift in a bit boundary, since you don’t
have control over time bases in other HART devices.
Figure 10. Clock Skew
SPI Interface and Internal Register
The NCN5192 also has an SPI interface that is used to
control the integrated DAC and set the configuration register
of the IC. This interface is accessible on the evaluation board
through connector IDC
5
.
The length of the SPI frame determines what the function
of the frame is. For setting the internal register, the SPI frame
has a length of 8 bits, containing all the bits of the internal
register. To set the output of the integrated DAC, a frame of
length 14 or 16 can be used, depending on which mode of the
DAC is used. For more information, see the section on the
integrated DAC.
Figure 11. SPI Interface (IDC
5
)
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