©
Semiconductor Components Industries, LLC, 2012
January, 2012
−
Rev. 2
1
Publication Order Number:
EVBUM2057/D
ECLTSSOP20EVB
Evaluation Board User's
Manual for High Frequency
TSSOP20
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 20
−
lead TSSOP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 20
−
lead TSSOP device
samples. The board provides a high bandwidth 50
W
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
•
Information on 20
−
lead TSSOP Evaluation Board
•
Assembly Instructions
•
Appropriate Lab Setup
•
Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay
−
Up
The 20
−
lead TSSOP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay
−
Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the 50
W
internal impedance in the oscilloscope as a termination for
ECL devices. The first layer or primary trace layer is 0.008
″
thick Rogers RO4003 material, which is designed to have
equal electrical length on all signal traces from the device
under the test (DUT) to the sense output. The second layer
is the 1.0 oz copper ground. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is the power plane (V
CC
& V
EE
)
and a portion of this layer is a ground plane. The fourth layer
is the secondary trace layer.
Figure 1. Top View of the 20
−
lead TSSOP Evaluation Board
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EVAL BOARD USER’S MANUAL
