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ON Semiconductor ECLTSSOP20EVB, Руководство пользователя

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ECLTSSOP20EVB

http://onsemi.com

2

Figure 2. Bottom View of the 20

−

lead TSSOP Evaluation Board

Bottom View

Expanded Bottom View

Figure 3. Evaluation Board Lay

−

up

LAY

−

UP DETAIL

4 LAYER

LAYER 1 (TOP SIDE) 1 OZ

ROGERS 4003 0.008 in

LAYER 2 (GROUND PLANE P1) 1 OZ

FR

−

4 0.020 in

LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ

FR

−

4 0.025 in

LAYER 4 (BOTTOM SIDE) 1 OZ

SILKSCREEN (TOP SIDE)

0.062 

$

 0.007

Board Layout

The 20

−

lead TSSOP evaluation board was designed to be

versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least eight possible configurable options. Table 1, list the
devices and the relevant configuration that utilizes this PCB

board. Lists of components and simple schematics are
located in Figures 6 through 12. Place SMA connectors on
J1 through J20, 50 

W

 chip resistors between ground pad and

Pin 1 pad through Pin 20 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01

m

F and C1, C2, and C3 are 0.1

Ăm

F); (See Figure 5).

Содержание ECLTSSOP20EVB

Страница 1: ...ll of Materials This manual should be used in conjunction with the device data sheet which contains full technical details on the device specifications and operation Board Lay Up The 20 lead TSSOP evaluation board is implemented in four layers with split dual power supplies see Figure 3 Evaluation Board Lay Up For standard ECL lab setup and test a split dual power supply is essential to enable the...

Страница 2: ...ed to be versatile and accommodate several different configurations The input output and power pin layout of the evaluation board is shown in Figures 4 and 5 The evaluation board has at least eight possible configurable options Table 1 list the devices and the relevant configuration that utilizes this PCB board Lists of components and simple schematics are located in Figures 6 through 12 Place SMA...

Страница 3: ...ECLTSSOP20EVB http onsemi com 3 Figure 4 Evaluation Board Layout Top View Bottom View ...

Страница 4: ...in 18 Pin 17 Pin 16 Pin 15 Pin 14 Pin 13 Pin 12 Pin 11 Figure 5 Enlarged Bottom View of the Evaluation Board Table 1 Configuration List Configuration Comments Device 1 See Figure 6 EP14 LVEP14 2 See Figure 7 EP17 LVEP17 3 See Figure 8 EP29 4 See Figure 9 EP40 5 See Figure 10 EP56 LVEP56 6 See Figure 11 EP57 7 See Figure 12 EP139 ...

Страница 5: ...desired device See Figure 5 It is recommended to solder 0 01 mF capacitors to C4 and C5 to reduce the unwanted noise from the power supplies C1 C2 and C3 pads are provided for 0 1 mF capacitor to further diminish the noise from the power supplies Adding capacitors can improve edge rates reduce overshoot and undershoot Termination All ECL outputs need to be terminated to VTT VTT VCC 2 0 V GND via a...

Страница 6: ...APACITOR 0 01 mF 0805 CHIP CAPACITOR 0 01 mF 0402 CHIP RESISTOR 50 W Table 3 Configuration 1 Device EP14 and LVEP14 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes No Yes No Resistor No No No No No No No No No No No Yes Yes Yes No Yes Yes...

Страница 7: ... 0 01 mF 0805 CHIP CAPACITOR 0 01 mF 0402 CHIP RESISTOR 50 W Table 4 Configuration 2 Device EP17 and LVEP17 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No N...

Страница 8: ...NANA JACK PLUG J3 J8 0603 CHIP CAPACITOR 0 1 mF J15 J18 J1 Table 5 Configuration 3 Device EP29 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes No Resistor Yes No Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No No No No Yes Yes No Powe...

Страница 9: ...vice EP40 Options 1 2 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Option 1 Internal Termination Resistor Configuration Connector No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes No Yes No Resistor No No No No No No No No No No No No No No No No No No No No Power VEE Gnd Gnd No No No No Gnd Gnd N...

Страница 10: ...BANANA JACK PLUG 0603 CHIP CAPACITOR 0 1 mF J15 J18 J1 J10 Table 7 Configuration 5 Device EP56 and LVEP56 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes No Resistor Yes Yes No Yes Yes Yes Yes No Yes Yes No No No No Yes Yes Yes No ...

Страница 11: ...ANA JACK PLUG J3 J8 0603 CHIP CAPACITOR 0 1 mF J15 J18 Table 8 Configuration 6 Device EP57 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector No Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No Yes Yes No Yes Yes No Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes No Power VCC No ...

Страница 12: ...RS BANANA JACK PLUG J3 0603 CHIP CAPACITOR 0 1 mF J15 J18 J10 Table 9 Configuration 7 Device EP139 Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Connector No Yes Yes Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes No Resistor No Yes Yes Yes Yes No Yes No Yes Yes No No No No No No No No No No Power ...

Страница 13: ...dual power supply is required enabling the 50 W internal impedance in the oscilloscope to be used as a termination of the ECL signals VTT VCC 2 0 V in split power supply setup VTT is the system ground VCC is 2 0 V and VEE is 3 0 V or 1 3 V see Table 10 2 Connect a signal generator to the input SMA connectors Setup input signal according to the device data sheet 3 Connect a test measurement device ...

Страница 14: ... Capacitor Johanson Dielectric 0603 0 01 mF 500R14Z100MV4E http www johansondielectrics com 0805 0 01 mF 500R15Z100MV4E 0603 0 1 mF 250R14Z101MV4E Chip Resistor Panasonic 0402 50 W 1 Precision Think Film Chip Resistor ERJ 2RKF49R9X http www panasonic com Evaluation Board ON Semiconductor TSSOP 20 Evaluation Board ECLTSSOP20EVB http www onsemi com Device Samples ON Semiconductor TSSOP 20 Package De...

Страница 15: ...ECLTSSOP20EVB http onsemi com 15 Figure 14 Gerber Files Top View Second Layer Ground Plane ...

Страница 16: ...ECLTSSOP20EVB http onsemi com 16 Figure 15 Gerber Files Third Layer Power and Ground Plane Left side VCC Right side VEE Middle Box Ground Bottom Layer ...

Страница 17: ...tems or any FDA Class 3 medical devices or medical devices with a similar or equivalent classification in a foreign jurisdiction or any devices intended for implantation in the human body Should you purchase or use the board for any such unintended or unauthorized application you shall indemnify and hold ON Semiconductor and its officers employees subsidiaries affiliates and distributors harmless ...

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