AGB3N0CS−GEVK
www.onsemi.com
3
Jumper Pin Location
The jumpers on boards start with Pin 1 on the leftmost side
of the pin. Grouped jumpers increase in pin size with each
jumper added.
Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side
Pins 1−4
Pin 1
Jumper/Header Functions & Default Positions
The P1 jumper/header configuration allows mode
selection to the Demo 2
×
Board. The 2−3 default jumper
position puts the Demo 2
×
in power safe mode, while the 1−2
jumper position puts the Demo 2
×
in Forced PWM mode.
The P5 jumper/header configuration allows for VDDIO
selection to the Demo 2
×
Board. The 2−3 default jumper
position connects VDDIO to +1.8 V, while the 1−2 jumper
position connects VDDIO to +2.8 V.
AGB3N0CS−GEVK Connectors
The adapter board supports has various different
connectors on-board, including a Demo 3 Headboard
connector, two MIPI/HiSPi connectors for the Demo 2
×
Board, the 13-pin Demo 2
×
Board connector, and 26-pin
Demo 2
×
Board connector.
Baseboard Connectors
The Demo 2
×
Baseboard connectors are shown in the
pinout in Tables 1 and 2. The Demo 2
×
connectors has
a 14-pin and 26-pin connector, as well as two MIPI/HiSPi
connectors.
Table 1. 26-PIN DEMO 2X BASEBOARD CONNECTOR FUNCTION DESCRIPTION (P3)
Pin
Name
Description
DIR
Comment
1
S_DATA8
Parallel Data8
I/O
Parallel Data Bit
2
S_DATA9
Parallel Data9
I/O
Parallel Data Bit
3
S_DATA10
Parallel Data10
I/O
Parallel Data Bit
4
S_DATA11
Parallel Data11
I/O
Parallel Data Bit
5
S_DATA12
Parallel Data12
I/O
Parallel Data Bit
6
S_DATA13
Parallel Data13
I/O
Parallel Data Bit
7
S_DATA14
Parallel Data14
I/O
Parallel Data Bit
8
S_DATA15
Parallel Data15
I/O
Parallel Data Bit
9
S_DATA6
Parallel Data6
I/O
Parallel Data Bit
10
S_DATA7
Parallel Data7
I/O
Parallel Data Bit
11
GND
Ground
PWR
12
GND
Ground
PWR
13
S_LINE_VALID
Parallel Line Valid
Out
Check Line Valid Signal
14
S_SP5
General Control Signal 5
Out
Signal @ +3.3 V Level
15
NOT USED
Not Used
NA
16
HEAD_RESET_L
Reset Signal to Sensor
In
Reset to Headboard Sensor
17
S_FRAME_VALID
Parallel Frame Valid
Out
Check Frame Valid Signal
18
HEAD_SDA
I
2
C Data to Sensor
I/O
Signal @ +3.3 V Level
19
HEAD_SCL
I
2
C Clock to Sensor
I/O
Signal @ +3.3 V Level
20
NOT USED
Not Used
NA
21
+5V0_HEAD
+5V0 Power Input
PWR
For Powering Up the Headboard
22
+5V0_HEAD
+5V0 Power Input
PWR
For Powering Up the Headboard
23
S_PIXCLK
Parallel Pixel Clock
In
Parallel Data Pixel Clock
24
GND
Ground
PWR
25
GND
Ground
PWR
26
MCLK
Master Clock
In
Master Clock from Demo 3 Board
