ADT7476A
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Table 59. REGISTER 0x42 − INTERRUPT STATUS REGISTER 2 (POWER-ON DEFAULT = 0x00)
Bit No.
Mnemonic
R/W
Description
[0]
12 V/VC
Read-only
A 1 indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read
of the status register only if the error condition has subsided. If Pin 21 is configured as VID5,
this bit is the VID change bit. This bit is set when the levels on VID0 to VID5 are different
than they were 11
m
s previously. This pin can be used to generate an SMBALERT whenever
the VID code changes.
[1]
OVT
Read-only
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This
bit is cleared on a read of the status register when the temperature drops below
THERM − T
HYST
.
[2]
FAN1
Read-only
FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is
not set when the PWM1 output is off.
[3]
FAN2
Read-only
FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is
not set when the PWM2 output is off.
[4]
FAN3
Read-only
FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is
not set when the PWM3 output is off.
[5]
F4P
Read-only
R/W
Read-only
When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped
below minimum speed or has stalled. This bit is not set when the PWM3 output is off.
When Pin 14 is programmed as the GPIO6 output, writing to this bit determines the logic
output of GPIO6. When GPIO6 is programmed as an input, this bit reflects the value read by
GPIO6.
If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set
when the THERM assertion time exceeds the limit programmed in the THERM timer limit
register (0x7A).
[6]
D1
Read-only
D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
[7]
D2
Read-only
D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 60. REGISTER 0x43 − VID/GPIO REGISTER (POWER-ON DEFAULT = 0x1F)
Bit No.
Mnemonic
R/W
Description
[4:0]
VID[4:0]/
GPIO[4:0]
R/W
The VID[4:0] inputs from the CPU indicate the expected processor core voltage. On
powerup, these bits reflect the state of the VID pins, even if monitoring is not enabled. When
Bit 4 of Configuration Register 5 (0x7C) = 1, these bits become general-purpose outputs. The
state of these bits then reflects the state of the appropriate GPIO pin.
[5]
VID5
R/W
Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, the VID5 bit always reads back 0
(power-on default).
[6]
THLD
R/W
Selects the input switching threshold for the VID inputs.
THLD = 0 selects a threshold of 1 V (V
OL
< 0.8 V, V
IH
> 1.7 V).
THLD = 1 lowers the switching threshold to 0.6 V (V
OL
< 0.4 V, V
IH
> 0.8 V).
[7]
VIDSEL
R/W
VIDSEL = 0 configures Pin 21 as the 12 V measurement input (Default).
Table 61. VOLTAGE LIMIT REGISTERS
(Note 1)
Register Address
R/W
Description (Note 2)
Power-On Default
0x44
R/W
2.5 V Low Limit
0x00
0x45
R/W
2.5 V High Limit
0xFF
0x46
R/W
V
CCP
Low Limit
0x00
0x47
R/W
V
CCP
High Limit
0xFF
0x48
R/W
V
CC
Low Limit
0x00
0x49
R/W
V
CC
High Limit
0xFF
0x4A
R/W
5.0 V Low Limit
0x00
0x4B
R/W
5.0 V High Limit
0xFF
0x4C
R/W
12 V Low Limit
0x00
0x4D
R/W
12 V High Limit
0xFF
1. Setting the Configuration Register 1 Lock bit has no effect on these registers.
2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit (
≤
comparison).
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