OMS MAXnet, Руководство пользователя

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CONTROL SIGNAL INTERFACE ABSOLUTE ENCODERS WITH SSI
MAXnet User’s Manual
4-8
4.9. ABSOLUTE ENCODERS WITH SSI
The MAXnet comes with two axes of configurable absolute encoders with SSI (Synchronous
Serial Interface) technology. By default the X and Y axes will have up to 12 bits of resolution of
absolute encoding. The MAXnet can have up to 10 axes of absolute encoders and up to 32 bits
of resolution per axis. The MAXnet provides a differential clock output through the I/0 port on the
MAXnet board to deliver clocking to an absolute encoder. With the MAXnet expansion board for 6
- 10 axes of absolute encoding, the differential clocking is provided out of the index signal
outputs. The clocking can be configured for the following frequencies: 31,250Hz, 62,500Hz,
125,000Hz, 250,000HGz, 500,000Hz, 1MHz, 2MHz, and 4MHz.
On the MAXnet board with I/O 0-7 available, typical use of absolute encoders require that clock+
and clock- be configured from the X-Axis through I/O 0-1, Y-Axis through I/O 2-3, Z-Axis through
I/O 4-5, and T-Axis through I/O 6-7. For the U-axis, clocking would also be configured from a
clock signal set through I/O 0-7. This requires that the clocking be shared between the U-axis
and another axis if more than four axes of absolute encoding are needed. Absolute encoders
sharing the same I/O output clocks have the requirement that the clock frequency is the same
and the bits resolution is the same.
On the MAXnet expansion board, the clock+ and clock- signals are provided via the index+ and
index- signals for each axis, not the I/O ports. Thus, there is no sharing of clocks needed or a
same frequency requirement between absolute encoders.
4.9.1. CONFIGURATION EXAMPLES
The following are two examples on how to configure the MAXnet for absolute encoding. The first
case is the standard MAXnet with two absolute encoders with up to 12 bits resolution. For this
example, the X axis is 12 bits resolution with a clock frequency at 125,000Hz, and the Y axis is 9
bits resolution with a clock frequency of 250,000Hz.
AX;
PSE;
ECA12,125000;
AY;
PSE;
ECA9,250000;
The second example calls for five absolute encoders, two axes at 16 bits resolution with a clock
frequency of 125,000Hz, one axis at 24 bits resolution with a clock frequency of 500,000Hz, and
two axes at 32 bits resolution at 250000Hz. This example also shows the use of clock sharing
with other absolute encoders with the same clock frequency and bits resolution.
AX;
PSE;
ECA16,125000;
AY;
PSE;
ECA16,125000;
AZ;
PSE;
ECA24,500000;
AT;
PSE;
ECA32,250000;
AU;
PSE:
ECA32,250000; Shares clocks with T-axis (I/O 6-7)