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113
AR Area
Section 6-4
AR 09
00
High-speed counter 1
commands
High-speed
Counter
Start Bit
OFF: Stops counter operation. The
high-speed counter PV is held.
ON: Starts counter operation. The
high-speed counter PV is not reset.
User
Enabled
01
High-speed
Counter
Reset Bit
OFF: If the counter reset method is
set to a software reset in the Unit
Setup Area (DM 6605 and DM
6607), the high-speed counter PV is
not cleared when internal I/O refresh
is performed in the Customizable
Counter Unit. If the counter reset
method is set to a phase Z + soft-
ware reset, phase-Z input is dis-
abled.
ON: If the counter reset method is
set to a software reset in the Unit
Setup Area (DM 6605 and DM
6607), the high-speed counter PV is
cleared when internal I/O refresh is
performed in the Customizable
Counter Unit. If the counter reset
method is set to a phase Z + soft-
ware reset, phase-Z input is
enabled.
02
Measure-
ment Start
Bit (mea-
surement
mode 1 or 2)
OFF: Measurement for high-speed
counter rate of change or frequency
measurement is disabled.
ON: Starts measurement for high-
speed counter rate of change or fre-
quency measurement.
Note 1:
Frequency measurement is
possible only with counter 1.
Note 2:
This bit is valid only when
the measurement mode set in the
Unit Setup Area (DM 6606 and
DM 6608) is set to high-speed
counter rate of change (measure-
ment mode 1) or frequency mea-
surement (measurement mode 2).
03
Measure-
ment Direc-
tion
Specifica-
tion Bit
(measure-
ment mode
2)
Specifies the direction (up or down)
of the pulse input for which fre-
quency measurement is performed.
OFF: Up
ON: Down
Note:
Be sure to set this bit before
turning ON the Measurement Start
Bit.
04
Range Com-
parison
Result Clear
Bit
OFF: The instruction execution
result (AR 10) or the output bit pat-
tern (AR 11) that is output when the
CTBL instruction is executed for a
range comparison on the high-
speed counter is not cleared.
ON: The instruction execution result
(AR 10) or the output bit pattern (AR
11) that is output when the CTBL
instruction is executed for a range
comparison on the high-speed
counter is cleared.
Address
Bits
Function
Details
Controlled
by
Forced
set/reset
Содержание CS1W-HCA12-V1
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Страница 20: ...xx Conformance to EC Directives 7...
Страница 38: ...18 Models and System Configurations Section 1 2...
Страница 78: ...58 Fail safe Circuits Section 3 5...
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Страница 204: ...184 Improved Instructions Section 7 14...
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Страница 240: ...220 Troubleshooting Flowcharts Section 9 5...
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