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Section 4-6
$&(
Example:
The High-speed Counter Unit is assigned Machine Number 2. You want to clear all
IOWR/IORD-instruction errors by issuing the IOWR-instruction with the Error
Clear command.
Note
Writing the Error Clear Command with IOWR is also supported for Simple
Counters (refer to 3-2-1
). This enables you to clear IORD/IOWR-
instruction errors that occurred after you have issued the IORD-instruction “Cap-
tured Counter Value” or the IORD/IOWR-instruction “Counter Value” to a Simple
Counter.
4-6
Interrupts
The status information of the 4 Digital Inputs and the 32 Outputs is exchanged with
the CS1-CPU every I/O refresh via the Special I/O Unit Area. The I/O refresh is
executed cyclically at the end of the Ladder Program or can be forced by I/O
refresh instruction. In both cases the CS1-CPU takes the initiative for a data-
exchange. In order for the High-speed Counter Unit to be able to report the status
information of the 4 Digital Inputs and 32 Outputs to the CS1-CPU, independent
from the I/O Refresh, all Digital Inputs and Outputs can be configured to generate
interrupts. Important events, indicated by a status change of the Digital Inputs and
the Outputs, can thus be reported as quickly as possible to the CS1-CPU.
Note
If you want the High-speed Counter to generate interrupts to the CS1-CPU the
Unit must be mounted on a CPU-backplane. If the Unit is mounted to an extension
backplane the Unit can not generate interrupts and all interrupts must be disabled.
4-6-1
Outputs Generating Interrupts
Enabling / Disabling
Interrupts
The 32 Outputs, divided in 4 Digital Outputs and 28 Soft Outputs, can all be con-
figured to generate interrupts to the CS1-CPU. If an Output is configured to gen-
erate interrupts, an interrupt is issued to the CS1-CPU at a rising and at a falling
edge of the corresponding bit in the Unit Output Pattern. For this purpose two
external interrupt tasks in the CS1-CPU are assigned to every Output. In the exter-
nal interrupt task you should write an appropriate (ladder) program that takes the
required action on the occurrence of an interrupt.
Item
IOWR
IORD
Control Code
No. of
Words
CC1
CC2
Clear Error(s)
Y
N
EC
00
1
IOWR(223)
#EC00
CC1= EC, CC2= 00
-
S=Not relevant (fill in valid constant, e.g. D0400
containing #0000)
#00010002
D= #0002 (Machine Number) and D+1= #0001 (# words)
W902-E2-03.book Seite 135 Donnerstag, 7. Oktober 2004 2:06 14
Содержание CS1W-CT021
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