Omnivision CameraChip OV9650, Руководство по внедрению

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42 Proprietary to OmniVision Technologies Version 1.1, December 7, 2004
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChip™ O
mni ision
10.2 Register Set
Table 10-2 provides a list and description of the Device Control registers contained in the OV9650.
For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses for
the OV9650 are 0x60 for write and 0x61 for read.
For factory-recommended settings, contact your local OmniVision FAE.
Note: All registers shown as reserved have no function or are very
sensitive analog circuit references. Use OmniVision reference values
(not default values).
Table 10-2. Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex) R/W Description
00 GAIN 00 RW
AGC[7:0] – Gain control gain setting
• Range: [00] to [FF]
01 BLUE 80 RW
AWB – Blue channel gain setting
• Range: [00] to [FF]
02 RED 80 RW
AWB – Red channel gain setting
• Range: [00] to [FF]
03 VREF 12 RW
Vertical Frame Control
Bit[7:6]: AGC[9:8] (see register GAIN for AGC[7:0])
Bit[5:3]: VREF end low 3 bits (high 8 bits at VSTOP [7:0]
Bit[2:0]: VREF start low 3 bits (high 8 bits at VSTRT [7:0]
04 COM1 00 RW
Common Control 1
Bit[7]: Reserved
Bit[6]: CCIR656 format
Bit[5]: QQVGA or QQCIF format. Effective only when QVGA
(register bit COM7 [4]) or QCIF (register bit COM7 [3]) output
is selected and related HREF skip option based on format
is selected (register COM1[3:2])
Bit[4]: Reserved
Bit[3:2]: HREF skip option
00: No skip
01: YUV/RGB skip every other row for YUV/RGB, skip 2
rows for every 4 rows for Raw data
1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows
for every 8 rows for Raw data
Bit[1:0]: AEC low 2 LSB (see registers AECHM for AEC[15:10] and
AECH for AEC[9:2])
05 BAVE 00 RW
U/B Average Level
Automatically updated based on chip output format
06 GEAVE 00 RW
Y/Ge Average Level
Automatically updated based on chip output format
07 RSVD 00 – Reserved