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52
Proprietary to OmniVision Technologies
Version 1.1, December 7, 2004
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChip™
O
mni
ision
9F
DBLC_Gb
00
RW
Digital BLC Gb Channel Offset Value
Bit[7:0]: Digital BLC Gb channel offset value
A0
DBLC_Gr
00
RW
Digital BLC Gr Channel Offset Value
Bit[7:0]: Digital BLC Gr channel offset value
A1
AECHM
40
RW
Exposure Value - AEC MSB 6 bits
Bit[7:6]: Reserved
Bit[5:0]: AEC[15:10] (see registers
for AEC[1:0])
A2
BD50ST
9D
RW
Banding Filter Value
(effective only when
[0] is low and
[0] is high)
A3
BD60ST
83
RW
Banding Filter Value
(effective only when
[0] is low and
[0] is low)
A4
COM25
00
RW
Common Control 25
Bit[7:0]: Reserved
A5
COM26
00
RW
Common Control 26
Bit[7:0]: Reserved
A6
G_GAIN
80
RW
Reserved
A7
VGA_ST
14
RW
Reserved
A8-AA
ACOM
XX
–
Reserved
NOTE:
All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Table 10-2. Device Control Register List (Continued)
Address
(Hex)
Register
Name
Default
(Hex)
R/W
Description