Omega Engineering PCI-DAS1001, Руководство пользователя

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3.0 HARDWARE CONNECTIONS
3.1 CONNECTOR PIN DIAGRAM
The PCI-DAS1000 series employ a 100 pin I/O connector. Please make accurate notes and pay careful attention to wire
connections. In a large system a misplaced wire may create hours of work ‘fixing’ problems that do not exist before the
wiring error is found.
3.2 CONNECTING SIGNALS TO THE PCI-DAS1000
The 100 pin connector provides a far greater signal density than the traditional 37 pin D type connector. In exchange for
that density comes a far more complex cable and mating connector. The C100-FF-2 cable is a pair of 50 pin ribbon cables.
At one end they are joined together with a 100 pin connector. From the 100 pin connector designed to mate with the
PCI-DAS1000 connector, the two 50 pin ribbon cables diverge and are terminated at the other end with standard 50 pin
header connectors. A CIO-MINI50 screw terminal board is the ideal way to terminate real word signals and route them into
the PCI-DAS1000. The BNC16/8 series provides convenient BNC connections to each of the analog inputs.
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A n alo g G ro un d 1
A n alo g In p ut C h 0 H ig h 2
A n alo g In p ut C h 0 L ow / 8 H ig h 3
4
5
6
7
8
9
1 0
11
1 2
1 3
1 4
1 5
1 6
1 7
A nalog G rou nd 1 8
N C 1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
C L K 4 3 9
G AT E 4 4 0
O U T 4 41
A /D E xte rn al P a ce r 42
N C 4 3
N C 4 4
A /D E xte rn al Trig ge r 45
4 6
4 7
P C + 5V 48
N C 4 9
P C G ro u nd 5 0
A n alo g In p ut C h 1 H ig h
A n alo g In p ut C h 1 L ow / 9 H ig h
A n alo g In p ut C h 2 H ig h
A n alo g In p ut C h 2 L ow / 1 0 H igh
A n alo g In p ut C h 3 H ig h
A n alo g In p ut C h 3 L ow / 11 H ig h
A n alo g In p ut C h 4 H ig h
A n alo g In p ut C h 4 L ow / 1 2 H igh
A n alo g In p ut C h 5 H ig h
A n alo g In p ut C h 5 L ow / 1 3 H igh
A n alo g In p ut C h 6H ig h
A n alo g In p ut C h 6 L ow / 1 4 H igh
A n alo g In p ut C h 7 H ig h
A n alo g In p ut C h 7 L ow / 1 5 H igh
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
D /A G N D 0 35
D /A O U T 0 3 6
D /A G N D 1 37
D /A O U T 1 3 8
N C
N C
5 1 D ig ita l A 0
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5 N C
7 6
7 7
7 8
7 9
8 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0 P C + 12 V
9 1 P C G ro u nd
9 2 P C -1 2V
9 3
9 4
9 5 A /D Interna l P a cer O u tp ut
9 6
9 7
9 8
9 9 N C
1 00 P C G ro u nd
D ig ital A 1
D ig ital A 2
D ig ital A 3
D ig ital A 4
D ig ital A 5
D ig ital A 6
D ig ital A 7
D ig ital B 0
D ig ital B 1
D ig ital B 2
D ig ital B 3
D ig ital B 4
D ig ital B 5
D ig ital B 6
D ig ital B 7
D ig ital C 0
D ig ital C 1
D ig ital C 2
D ig ital C 3
D ig ital C 4
D ig ital C 5
D ig ital C 6
D ig ital C 7
N C
N C
N C
N C
C L K 6
G AT E 6
O U T 6
N C
N C
C L K 5
G AT E 5
O U T 5
N C
P C G roun d
N C
N C
N C
N C
N C
P C I-D A S 1 00 0 C on ne cto r D iag ram