OKIFAX 610, Руководство по обслуживанию

Страница: 114 / 147

Table 8.1.1-3 XFC Memory Map
Chip select Address (Hex) External to XFC Internal to XFC
CS0 000000-007FFF SRAM
00E000-00FC00 Internal RAM
CS1 00FC00-00FDFF I/O (N/C)
00FE00-00FEFF Internal registers
MCS 00FF00-00FFFF Modem
CAS0 400000-4FFFFF DRAM
CAS1 500000-5FFFFF DRAM
ROMCS FE0000-FFFFFF ROM
8.1.1.1 Bus Cycle Timing
The processor and external bus cycle timing is defined by bclk (an internal signal). bclk is
referenced to TSTCLK which is derived by dividing SYSCLK by 2 as shown in Figure 8.1.1.1-1.
bclk can be extended low (halted state) or stretched high (wait state) by external and internal
conditions. Both halt and wait state are indicated on the external pin /WAIT.
A standard bus cycle begins at the falling edge of TSTCLK and ends at the falling edge of the next
TSTCLK. Some memory and peripheral devices require extended bus cycle, which is added with
wait states. Wait states can be created with programmable control for external chip selects
(/ROMCS. /MCS, /CS[0:1]), and the DRAM controller (/CAS[0:2]).
The bus cycle can be halted by an access conflict (i.e., a CPU or DMA access to DRAM coincident
with a DRAM refresh, or a CPU access to the RAM when a DMA access of the same RAM is in
progress). When the bus cycle is stopped, halt states are added in increments of TSTCLK. When
halt condition is released, the bus cycle resumes at the next TSTCLK rising edge.
bclk
TSTCLK
Bus Cycle
/WAIT
1 halt state
1 wait state
Figure 8.1.1-1 Bus Clock
8.1.1.2 External Bus Signal Timing
External bus clock and control timing is shown in Figure 8.1.1-2, while external bus data access
timing is shown in Figure 8.1.1-3, and Table 8.1.1-4 provides the signal timing parameters for both
of these figures.