Oki TF-300P, Руководство по обслуживанию на месте

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6-10
Parameter Symbol Min. Max. Units
REGDMA delay (DMA access) tDMD - 30
tSL+10
ns
WAITn delay tWSD - 30
tSL+12
ns
RDn,WRn delay tSD - 5 ns
RDn,WRn delay (Delay On=1) tSDD - 30
tSL+10
ns
RDn,WRn delay(Delay On=2,3) tSDD - 12 ns
WRn delay (Early Off) tSDE - 30
tSL+10
ns
Address delay tAD - 30
tSL+10
ns
Chip Select delay tCSD - 30
tSL+12
ns
Chip select (CSn[4:3]) delay tCGD - 10
Data setup (Read) tDS 12 - ns
Data hold (Read) tDHR 0 - ns
Data delay (Write) tDDW - 20 ns
Data delay(Internal access) tDDI - 30 ns
Data hold (Write, Internal
access) tDH tSL-10 - ns
Notes :
1. Valid value is whichever is the greater of the 2 values listed.
2. Test Conditions: 5.0V +5%/-10%, 70
¢ J
, 50pF on all pins.
6.1.2.3. DRAM Controller
The DRAM chip provided is 1 Mega by 4 bits with maximum access time 100ns. Up to 1 column
chip selects,
/CAS0 , are supported to access total 1 Mega bytes. For basic memory of 1Mega bytes,
2 DRAM chips are provided, while for extended memory, 2 more chips are provided.
Address bus of DRAM are physically connected to address bit A0 to A9 of FC200(-M). Row
addresses are gated onto the DRAM address bus first, followed by column addresses. The
following operation modes are supported: bytes access mode, early write mode and normal read
mode. One wait state is inserted in each DRAM bus cycle.
DRAM refresh is performed automatically, but only /CAS before /RAS operation is supported.
Refresh cycle time per 1024 cycles is 125ms. During power on when it is time to refresh DRAM and
they are not being accessed, the refresh cycle starts. When power down, no DRAM access occur,
and DRAM can’t backup the data.
6.1.2.4. CPU Interrupts
There are two ways to interrupt CPU, maskable interrupt ( /MIRQ ) and non-maskable interrupt NMI
( /DEBUG , /PWRDWN ). Modem interrupt /MIRQ must hold active until the CPU processes the
request. The input /PWRDWN is OR'ed with the input /DEBUG and then synchronized before NMI
input. An active NMI signal branches program execution to the address stored in NMI vector. When
NMI represents power down, indicated by
/PWRDWN low, the NMI control firmware performs the
necessary maintenance operation and then enable lockout register to protect battery backed-up