Oki TF-300P, Руководство по обслуживанию на месте, Страница: 46 / 137

6-7
6.1.2.1. Bus Cycle Timing
The processor and external bus cycle timing is defined by
bclk
(an internal signal).
bclk
is
referenced to TSTCLK which is derived by dividing SYSCLK by either 2 or 3,as shown in Figure
8.1.1.1-1 and Figure 8.1.1.1-2,respectively. bclk can be extended low (halted state) or stretched
high (wait state) by external and internal conditions that are described later. Both halt and wait state
are indicated on the external pin WAITn.
A standard bus cycle begins at the falling edge of TSTCLK and ends at the falling edge of the next
TSTCLK. Some memory and peripheral devices require extended bus cycle, which is accomplished
by adding wait states. During wait states, the WAITn signal is activated. Wait states can be created
with programmable control provided for external chip selects (ROMCSn, MCSn, CS [5:0]n), by the
DRAM controller (CAS[1:0]n),and with the external RDY input pin. The wait states created by the
RDY input are added to the wait states generated by the chip select control logic.
The bus cycle can be halted by BE pin or by an access conflict (i.e., a CPU or DMA access to
DRAM coincident with a DRAM refresh, or a CPU access to the RAM when a DMA access of the
same RAM is in progress). When the bus cycle is stopped, Halt states are added in increments of 1
TSTCLK . When the Halt condition is released, the bus cycle resumes at the next TSTCLK rising
edge Figure 6-2 shows an example of a bus cycle with 1Halt state.
With one hal t state With one wait state
bclk
TSTCLK
Bus Cycle
WAITn
1060F4-2
Figure 6-1 Bus Cycle (Divide by 2)