Oki ML63611, Руководство пользователя

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ML63611 User’s Manual
Chapter 5 Clock Generator Circuit (OSC)
5 – 7
OPTION B (D): 1.5 V (3.0 V), With regulator
circuit for LCD bias
OPTION A (C): 1.5 V (3.0 V), Without regulator
circuit for LCD bias
5.7 System Clock Select Timing
After system reset, the system clock is TBCCLK.
When high-speed operation is necessary, switch the system clock to HSCLK.
A flowchart of system clock operation is shown below.
TBCCLK
System clock status
HSCLK
After system reset, the low-
speed clock generator output
is the system clock.
(1) High-speed clock oscillation mode select
OSCSEL = “0” : RC oscillation mode
(initial value)
OSCSEL = “1” : Ceramic oscillation mode
ENOSC (bit 1 of FCON) = “0”
(2) High-speed clock oscillation stop
ENOSC = “0” : Stop high-speed clock oscillation
(initial value)
ENOSC = “1” : Start high-speed clock oscillation
Software processing Software processing
ENOSC (bit 1 of FCON) = “1”
(2) High-speed clock oscillation start
Wait:
When RC oscillation mode selected:
300 µs or more
When ceramic oscillation mode selected:
10 ms or more
CPUCLK (bit 0 of FCON) = “1”
(3) High-speed clock oscillation output select
CPUCLK (bit 0 of FCON) = “0”
(1) Low-speed clock oscillation output select
(Low-speed clock generator circuit output)
(High-speed clock generator circuit output)
ENOSC = “0” : Stop high-speed clock oscillation
(initial value)
ENOSC = “1” : Start high-speed clock oscillation
CPUCLK = “0” : Low-speed clock oscillation output
(initial value)
CPUCLK = “1” : High-speed clock oscillation output
CPUCLK = “0” : Low-speed clock oscillation output
(initial value)
CPUCLK = “1” : High-speed clock oscillation output
OSCSEL (bit 2 of FCON) setting