
Chapter 2. Functions
2-12
1FFH
200H
201H
202H
Specifying an address of any, a
comparison value of 3, and a
count of 1 produces a break one
instruction after the once
execution of the MOV [HL],A
instruction at address 203H,
that is, after the INCB HL
instruction at address 204H.
203H
204H
205H
RAM write
instruction
MOV CBR,#3H
MOV A,#3H
MOV H,#0FH
MOV L,#0FH
NOP
INCB HL
MOV [HL],A
The break timing is not immediately after the instruction satisfying the break condition, but an additional
instruction later.
There is a bit mask parameter for extending data checking to multiple (or even all) comparison values.
Specifying a code memory address produces a break only if the instruction at that address writes to a
data memory address.
n
Note 1
n
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RAM data match breaks are available over the entire data memory address space—even SFR
addresses with reserved bits (bits that ignore writes and always return “1”) and addresses with
read-only bits.
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n
Note 2
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RAM data match breaks check only writes by instructions. RAM modifications by timers and
other circuits are ignored.
________________________________________________________________________________________________________________________________
n
Note 3
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A RAM data match break request remains in effect until the next write instruction. To resume
emulation under the same break conditions, write somewhere in RAM using data that does not
produce another break.
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(4) RAM address match break
Execution breaks one instruction after instructions have written the specified number of times to the
specified data memory address.
Содержание Dr.63514
Страница 4: ...Table of Contents...
Страница 7: ...Preface...
Страница 15: ...Chapter 1 Overview...
Страница 22: ...Chapter 2 Functions...
Страница 69: ...Chapter 3 Setting Up and Starting Up...
Страница 76: ...Chapter 4 Additional Usage Notes...
Страница 88: ...Appendices...
Страница 94: ...Appendices A 7 black brown red orange yellow green blue purple Figure A 4 Probe cable layout...