
TECHNICAL INFORMATION
__________________________________
The following tables summarize pin assignments
for the I/O channel connectors.
I/O Channel (A-Side)
I/O Pin
Signal Name
I/O
A1
-I/O CH CK
I
A2
SD7
I/O
A3
SD6
I/O
A4
SD5
I/O
A5
SD4
I/O
A6
SD3
I/O
A7
SD2
I/O
A8
SD1
I/O
A9
SD0
I/O
A10
-I/O CH RDY
I
A11
AEN
O
A12
SA19
I/O
A13
SA18
I/O
A14
SA17
I/O
A15
SA16
I/O
A16
SA15
I/O
A17
SA14
I/O
A18
SA13
I/O
A19
SA12
I/O
A20
SA11
I/O
A21
SA10
I/O
A22
SA9
I/O
Содержание Hippo-SX
Страница 1: ...H I P P O S X...
Страница 21: ...GENERAL FEATURES __________________________________...
Страница 34: ...CONFIGURING THE SYSTEM __________________________________...
Страница 36: ...CONFIGURING THE SYSTEM __________________________________ 6 5 Vdc...
Страница 43: ...TECHNICAL INFORMATION __________________________________...
Страница 59: ...THIS PAGE IS INTENTIONALLY LEFT BLANK...
Страница 61: ...THIS PAGE IS INTENTIONALLY LEFT BLANK...
Страница 66: ...Appendix E System Board Layout _______________________________...
Страница 67: ...Appendix F Memory Expansion Card Layout _______________________________...
Страница 68: ...Appendix G Hippo Cache Card Layout _______________________________...