Octek Hippo-SX, Руководство пользователя

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GENERAL FEATURES
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If a read miss occurs, the CPU will initiate a burst
mode read operation. In burst mode read operation, CPU
performs four successive read operations each of which
takes only one cycle. Total 128 bits data are fetched into
the CPU's internal cache. Since burst mode read
operation is very fast, the traffic of the CPU bus is greatly
reduced and the bus is available to other bus masters,
such as DMA controller.
By eliminating the access to external bus,
operations with the internal cache can be completed in a
single cycle. 80386DX at least needs two cycles for an
operation. To further increase the rate of data transfer
inside the CPU, the internal bus of the cache memory is
increased to 128 bits, which is four times of the external
bus. Since, in most of the time, the CPU is using the
internal cache, the large bus size substantially improves
the overall performance.
When the CPU writes data to the main memory,
the data is first stored in a write buffer. There are four
write buffers. When the external bus is idle, data will be
sent to the main memory. If all buffers are filled, it can
start write operation in burst mode. Since the internal
cache is updated immediately, the CPU need not
suspend its operation and there is no need to wait for the
external device to update the main memory.
Many often-used instructions are executed in a
clock cycle and some instructions are modified to take
fewer cycles than in 80386DX. On the contrary,
80386DX may take two to three more cycles for the
same instruction. The CPU contains an advanced
instruction pipeline structure and a 32-byte code queue
to speed up the execution.
80486SX includes all the functions of 80386DX
and is able to support sophisticated software and
operation systems which are widely employed now. It is
able to operate in real mode, protected mode and virtual
8086 mode. A new addressing mechanism allows
switching between modes more efficiently. Hence