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NXP Semiconductors

TR1329

Systems & Applications

TR1329

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2018. All rights reserved.

User Manual

Rev. 01.20

— 31 January 2018

4 of 19

1.1 Acronyms

Table 1.

Acronyms used in the document

Acronym

Description

BAT

Battery

DC

Direct Current

GND

Ground

MAC

Medium Access Controller

MDI

Medium Dependent Interface

MII

Medium Independent Interface

PHY

Physical

uC

Microcontroller

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Содержание TJA1100

Страница 1: ... User Guide Rev 01 20 31 January 2018 User Manual Document information Info Content Title TJA1100 Customer Evaluation Board User Guide Author s Steffen Lorenz Simon Zhu Department Systems Applications Keywords TJA1100 100BASE T1 Ethernet PHY ...

Страница 2: ...ice addresses please send an email to salesaddresses nxp com Revision history Rev Date Description 1 0 20160112 Initial version 1 1 20160816 Updated for board revision V6 with latest EMC filter and ESD protection Fig 1 2 4 5 6 7 8 updated Section 4 1 schematics updated 1 2 20180131 Updated for board revision V7 with latest MDI circuitry and new connector CE compliancy statement added Fig 1 2 3 4 5...

Страница 3: ...tance to a host controller board the bus interface MDI including a srew terminal SMKDS connector as well as needed components for the power supply and operation Further information is given in the following sections Please note the evaluation board has been designed for functional evaluation of the PHY in your environment The evaluation board is not intended for EMC or compliance qualification mea...

Страница 4: ...aimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 4 of 19 1 1 Acronyms Table 1 Acronyms used in the document Acronym Description BAT Battery DC Direct Current GND Ground MAC Medium Access Controller MDI Medium Dependent Interface MII Medium Independent Interface PHY Physical uC Microcontroller ...

Страница 5: ...e Fig 2 Fig 2 Pin 1 Location 2 2 Jumper Settings 2 2 1 Bit Strapping The TJA1100 has several configuration pins for a pre configuration during startup The following tables give an overview of the related jumpers and possible configurations as shown also in Fig 3 At the PCB Fig 4 the orientation for High H and Low L is marked Please note all pre configuration except for the PHY addresses can be ove...

Страница 6: ...en the TJA1100 is configured for Autonomous operation the PHY will automatically enter Normal mode and activate the link on power on without further interaction with a host controller Table 3 Bit Strapping Master Slave Configuration Jumper Function Master Slave JP18 Configuration of CONFIG0 H L Table 4 Bit Strapping Managed autonomous Operation Jumper Function Managed Autonomous JP19 Configuration...

Страница 7: ...R1329 Systems Applications TR1329 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 7 of 19 Fig 3 Bit Strapping Jumper Settings ...

Страница 8: ...R1329 Systems Applications TR1329 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 8 of 19 Fig 4 Bit Strapping Jumpers on PCB ...

Страница 9: ...ghts reserved User Manual Rev 01 20 31 January 2018 9 of 19 2 3 Connectors LEDs 2 3 1 MII Connector For the MII a double row 40 pin 2 54x2 54mm male header P1 Fig 5 is used At the PCB Fig 5Error Reference source not found the pinning order is marked The pinning order of the MII connector is given in 0 Fig 5 MII Connector Location and Pinning Order ...

Страница 10: ...in 1 TJA1100_WAKE TJA1100_INH 2 3 TJA1100_RSTN GND 4 5 TJA1100_INT GND 6 7 TJA1100_MDC GND 8 9 TJA1100_MDIO GND 10 11 TJA1100_EN GND 12 13 TJA1100_TXER GND 14 15 TJA1100_TXD0 GND 16 17 TJA1100_TXD1 GND 18 19 TJA1100_TXD2 GND 20 21 TJA1100_TXD3 GND 22 23 TJA1100_TXEN GND 24 25 TJA1100_TXCLK GND 26 27 TJA1100_RXCLK GND 28 29 TJA1100_RXD0 GND 30 31 TJA1100_RXD1 GND 32 33 TJA1100_RXD2 GND 34 35 TJA110...

Страница 11: ...t is subject to legal disclaimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 11 of 19 2 3 2 MDI Connector For the MDI interface a two position PCB terminal connector SMKDS 5 2 2 54 from Phoenix Contact is used and the details are given in Fig 6 Fig 6 MDI Pinning Order ...

Страница 12: ...be used to evaluate the status of the Board Fig 7 shows all the LEDs on the Board and Table 7 sums up the meaning of each LED Fig 7 LEDs on the Board Table 7 Descriptions of LEDs LED Description LED1 TJA1100 3V3 Power Supply Status ON 3V3 is present LED2 TJA1100 Local Wake up Status Flashing a Local Wake up is detected LED3 TJA1100 Battery Power Supply Status ON Battery is present LED4 TJA1100 1V8...

Страница 13: ...ems Applications TR1329 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 13 of 19 3 Reference 1 TJA1100 Datasheet Version 3 23 May 2017 ...

Страница 14: ...pplications TR1329 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 14 of 19 4 Appendix 4 1 The TJA1100 Customer Evaluation Board Schematics ...

Страница 15: ... Semiconductors TR1329 Systems Applications TR1329 All information provided in this document is subject to legal disclaimers NXP B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 15 of 19 ...

Страница 16: ...iconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these produc...

Страница 17: ...P B V 2018 All rights reserved User Manual Rev 01 20 31 January 2018 17 of 19 6 List of figures Fig 1 Customer PHY Board Top View 3 Fig 2 Pin 1 Location 5 Fig 3 Bit Strapping Jumper Settings 7 Fig 4 Bit Strapping Jumpers on PCB 8 Fig 5 MII Connector Location and Pinning Order 9 Fig 6 MDI Pinning Order 11 Fig 7 LEDs on the Board 12 ...

Страница 18: ...rved User Manual Rev 01 20 31 January 2018 18 of 19 7 List of tables Table 1 Acronyms used in the document 4 Table 2 Bit Strapping PHY address 6 Table 3 Bit Strapping Master Slave Configuration 6 Table 4 Bit Strapping Managed autonomous Operation 6 Table 5 Jumper Settings for Bit Strapping 6 Table 6 MII Connector Pinning 10 Table 7 Descriptions of LEDs 12 ...

Страница 19: ...salesaddresses nxp com Date of release 31 January 2018 Document identifier TR1329 8 Contents 1 Introduction 3 1 1 Acronyms 4 2 Board Setup 5 2 1 PHY Assembly 5 2 2 Jumper Settings 5 2 2 1 Bit Strapping 5 2 3 Connectors LEDs 9 2 3 1 MII Connector 9 2 3 2 MDI Connector 11 2 3 3 LEDs 12 3 Reference 13 4 Appendix 14 4 1 The TJA1100 Customer Evaluation Board Schematics 14 5 Legal information 16 5 1 Def...

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