Highest priority is given to the high-fidelity analog front end supplies VDD_HV_RAW and VDD_HV_DAC, as their
decoupling must be prioritized to maintain analog signal integrity. VDD_HV_ADRREF0, VDD_HV_ADREF1, and
VDD_HV_ADC is the SAR analog-to-digital converters reference and power supply decoupling. Clean supplies are vital to
ensure that the highest accuracy is achieved with the ADCs. The supply for the system PLL is prioritized as this helps to
ensure reliable and stable operation from the internal PLL circuit.
Medium priority is given to VDD_LV_CORE, VDD_LV_DRFPLL, VDD_LV_AURORA, VDD_HV_PMU,
VDD_LV_DPHY and VDD_HV_FLA. VDD_LV_CORE is the main supply for the on-chip digital logic and this is
prioritized as it affects the largest amount of logic on the device. VDD_LV_AURORA powers the high speed Nexus Aurora
pins and noise on this domain would affect the quality of the output. VDD_HV_PMU is the power management unit supply
and VDD_LV_DPHY is the MIPI-CSI2 DPHY supply. The MIPI-CSI2 DPHY is a high speed module which requires
minimal noise in order to acheive the specified performance levels. VDD_HV_FLA is the input supply for the flash memory.
A good supply to the flash memory ensures reliable flash programming and erasing.
VDD_LV_LFASTPLL powers the PLL for the LFAST/SIPI communication interface.
and VDD_LV_IO drive GPIO and other external communication interfaces. Although it is still important that these supplies
have a clean power signal, the hardware they power is less affected by noise and they are considered of lower priority.
When completing the layout of decoupling capacitors care should be taken to reduce the volume of the space in the
transmission line between the device and the capacitor, which results in faster response to energy requests from the device.
The capacitor should always be the closest to the device so that the energy comes from the capacitor and not from the power
trace, as illustrated in the figure below.
Figure 1. Decoupling capacitor placement recommendation
3.3 Power management controller
The S32R family has a dedicated module for configuration and monitoring of power supplies, enable signals, internal
component trimming, and power-on reset generation. The Power Management Controller (PMC) consists of an analog block
and a supporting digital interface that provides control over the analog components. The PMC chapter in the device reference
manual explores the digital block in depth.
4. This interface is not present on the S32R372 device, but the supply name remains the same for the 257MAPBGA
package to avoid confusion, and is not present on the 141MAPBGA package.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
6
NXP Semiconductors
