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NXP Semiconductors
S32K3X4EVB-Q172 HWUM
S32K3X4EVB-Q172 | S32K3X4EVB-S172 - Hardware User Manual
S32K344EVB-Q172 | -S172 HWUM
All Information provided in this document is subject to legal disclaimers
© NXP B.V. 2020. All rights reserved
NXP Semiconductors
REV A
– 10/2021
Page
6
of
31
Interface
S32K3X4
EVB-
Q172
S32K3X4
EVB-
S172
Reference / Signal
Default
Configuration
Description/Comment
●
●
V15_MCU
External NPN
Transistor
The V15_MCU domain is routed to the VCORE from the
FS26
Ethernet
●
Ethernet MII/RMII
SABRE Connector
MII/RMII
Enabled
All Ethernet MII/RMII signals are routed to ENET SABRE
connector, only for the
S32K3X4EVB-S172,.
●
10/100 TBase
Ethernet Phy
MII/RMII
Enabled
All Ethernet MII/RMII signals are routed to 10/100 T-Base
Physical layer with RJ45 connector, only for the
S32K3X4EVB-Q172.
QSPI-A
Memory
●
●
Enabled
The MCU signals to the QSPI-A Memory Interface are
enabled
OnBoard
Debugg
●
●
PTA15
PTA15/LPUART6_RX is routed to OpenSDA for serial
interface
PTA16
PTA16/LPUART6_TX is routed to OpenSDA for serial
interface
TRACE
●
●
J12
Disabled
The TRACE Signals are disabled as DEFAULT in the 20pin
cortex Debug D ETM Connector
CAN
Interface
●
●
TJA1023/CAN0
PTA6
PTA26 is routed to the CAN0_RX signal
PTA7
PTA27 is routed to the CAN0_TX
PTC23
PTC23 is routed to the CAN0_ERRN
PTC21
PTCCAN0_EN
PTC20
CAN0_STB
LIN
Interface
●
●
LIN1
PTB9
LPUART9_RX is routed to LIN Phy0
PTB10
LPUART9_TX is routed to LIN Phy0
LIN2
PTB28
LPUART5_RX is routed to LIN Phy1
PTB27
LPUART5_TX is routed to LIN Phy1
User Push
Buttons
●
●
SW4
Disabled
Active Low,
SW5
PTB19
Active Low, before PTA1
User LEDs
●
●
D13
PTA29
Red
PTA30
Green
PTA31
Blue
ADC
Potentiometer
s
●
●
ADCPOT0
PTA11
ADCPOT0 [R293] is routed to PTA11 -
ADC1_S10
ARDUINO
●
●
-
-
6 S32K3X4EVB-Q172 | -S172 - Startup
Follow these steps to connect and power on the board
1. Carefully unpack the S32K3X4EVB-Q172 and observe ESD preventive measures while handling the K3 development board.
2. Connect necessary cables between host PC and EVB board prior to applying power to the EVB.
3. The power-ON sequence for the EVB must be as follows: