UM10492
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© NXP Semiconductors N.V. 2015. All rights reserved.
User manual
Rev. 1.1 — 16 March 2015
11 of 14
NXP Semiconductors
UM10492
PTN3460 eDP to LVDS bridge IC application board
6. Stuffing
options
6.1 PTN3460
NXP
pinning
6.2 Stuffing
locations
Fig 5.
PTN3460 pinning
1µ
F
4
.7µF
0.
1
µF
0.
1µ
F
FB
0.
1
µ
F
0.
01
µF
FB
4.7
µ
F
0.
1
µF
0.
1µ
F
0.
1µ
F
VDD18
VDD33
VDD18
VDD18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PTN3460
0
.1µF
Table 4.
Stuffing locations
Location
Function/value
PTN3460 (default pinning)
R16
Join +3V3_IO with +3V3_LDO
no load
R17
Pin 27 = CFG4/TDO
load
R18
Pin 26 = BKLTEN_PTN
load
R19
Pin 28 - PWMO_PTN
load
R20
Pin 32 = LVSDE_N_PTN
load
R21
Pin 31 = LVSDE_P_PTN
load
R22
Pin 32 = PWMO
no load
R23
Pin 31 = BKLTEN
no load
R24
+3V3_LDO for pin 13, 14
load
R25
Pin 28 = GND
no load
R26
Pin 26 = GND
no load
R27
Pin 27 = GND
no load
C27
1
F for RST_N line
no load
C22
0.47
F
no load