UM10541
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
5 of 7
NXP Semiconductors
UM10541
NVT2008PW and NVT2010PW demo boards
2.2 Jumper and header functions
The functions of the jumpers and headers on these demo boards are shown in
Table 1
.
3. References
[1]
NVT2008; NVT2010, “Bidirectional voltage-level translator for open-drain and
push-pull applications” —
Product data sheet; NXP Semiconductors;
www.nxp.com/documents/data_sheet/NVT2008_NVT2010.pdf
[2]
AN11127, “Bidirectional voltage level translators NVT20xx, PCA9306,
GTL2000, GTL2002, GTL2003, GTL2010” —
application note;
NXP Semiconductors;
www.nxp.com/documents/application_note/AN11127.pdf
Table 1.
Header descriptions for NVT2008PW (OM13317) and NVT2010PW (OM13324) demo boards
Jumper/header
Function
Notes
J1 (3-pin)
Device switch enable or disable
control
Short pins 2 and 3 to enable the NVT2008PW or NVT2010PW
device (default). When pins 1 and 2 are shorted, the device is
disabled.
J2 (12-pin)
Low voltage VREFA, GND and
An I/O signal connect pins
Pin 1 = VREFA: low voltage power.
Pin 12 = GND: low voltage ground.
A[1:8] are low voltage signals for NVT2008PW.
A[1:10] are low voltage signals for NVT2010PW.
J3 (3-pin)
Connects 10 k
Ω
pull-up resistors to
VREFA on low voltage side for
VREFB
−
VREFA < 1 V
application required
Short pins 1 and 2 to connect 10 k
Ω
pull-up resistors to VREFA
on low voltage side (default).
Remark:
Pins 1 and 2 must be open and 10 k
Ω
pull-up resistors
must be removed when VREFB
−
VREFA
≥
1 V.
J4 (12-pin)
High voltage VREFB, GND and
Bn I/O signal connect pins
Pin 1 = VREFB: high voltage power.
Pin 12 = GND: high voltage ground.
B[1:8] are high voltage signals for NVT2008PW.
B[1:10] are high voltage signals for NVT2010PW.
