26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1
When SC[VREFEN] = 1, the Voltage Reference is enabled, and different modes should
be set by the SC[MODE_LV] bits.
26.3.2.1 SC[MODE_LV]=00
The internal VREF bandgap is enabled to generate an accurate 1.2 V output that can be
trimmed with the TRM register's TRIM[5:0] bitfield. The bandgap requires some time for
startup and stabilization. SC[VREFST] can be monitored to determine if the stabilization
and startup is complete when the chop oscillator is not enabled.
If the chop oscillator is being used, the internal bandgap reference voltage settles within
the chop oscillator start up time, Tchop_osc_stup.
The output buffer is disabled in this mode, and there is no buffered voltage output. The
Voltage Reference is in standby mode. If this mode is first selected and the low power or
high power buffer mode is subsequently enabled, there will be a delay before the buffer
output is settled at the final value. This is the buffer start up delay (Tstup) and the value is
specified in the appropriate device data sheet.
26.3.2.2 SC[MODE_LV] = 01
The internal VREF bandgap is on. The high power buffer is enabled to generate a
buffered 1.2 V voltage to VREF_OUT. It can also be used as a reference to internal
analog peripherals such as an ADC channel or analog comparator input.
If this mode is entered from the standby mode (SC[MODE_LV] = 00, SC[VREFEN] = 1)
there will be a delay before the buffer output is settled at the final value. This is the buffer
start up delay (Tstup) and the value is specified in the appropriate device data sheet. If
this mode is entered when the VREF module is enabled then you must wait the longer of
Tstup or until SC[VREFST] = 1 when the chop oscillator is not enabled. If the chop
oscillator is being used, you must wait the time specified by Tchop_osc_stup (chop
oscillator start up time) to ensure the VREF output has stabilized.
In this mode, a 100 nF capacitor is required to connect between the VREF_OUT pin and
VSSA.
Chapter 26 Voltage Reference (VREFV1)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
429
Содержание MKL27Z128VFM4
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