NXP Semiconductors MC9S08LG16, Справочное руководство

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MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 259
Chapter 13
Serial Communications Interface (S08SCIV4)
13.1 Introduction
Figure 13-1 shows the MC9S08LG32 series block diagram with the SCI highlighted.
13.1.1 Module Instances
The MC9S08LG32 series MCUs contain two SCI modules: SCI1 and SCI2. The memory map, pins,
interrupts, etc. for the two modules can be differentiated using the SCI1 and SCI2 nomenclature.
13.1.2 Module Configuration
The SCI module pins, TX1, RX1, TX2, and RX2 can be repositioned under software control using TX1,
RX1, TX2, and RX2 bits in PINPS4 and PINPS3 as shown in
Table 13-1 . TX1, RX1, TX2, and RX2 bits
in PINPS4 and PINPS3 selects which general-purpose I/O ports are associated with IIC operation.
13.1.3 SCI Clock Gating
The bus clock to the SCI can be gated on and off using the SCI bit in SCGC1. This bit is cleared after any
reset, which disables the bus clock to this module. To conserve power, the SCI bit can be cleared to disable
the clock to this module when not in use. For more details, see
Section 5.7, “Peripheral Clock Gating .”
Table 13-1. SCI Position Options
TX1/RX1/TX2/RX2 Port Pin for TX1 Port Pin for RX1 Port Pin for TX2 Port Pin for RX2
0 (default) PTF0 PTF1 PTA3 PTA4
1 PTH5 PTH4 PTI1 PTI0