NXP Semiconductors
MC56F80000-EVKUM
MC56F80000-EVK Board User Manual
2.4 SPI Flash interface
The MC56F80748 supports one queued serial peripheral interface (QSPI) controller that
provides:
•
Maximum of 25 Mbit/s baud rate
•
Full-duplex operation
•
Master and slave modes
The QSPI controller signals are multiplexed with the GPIO (Group C) pin signals.
On the MC56F80000-EVK board, QSPI controller connects to the 512 kbit Macromix
MX25L512E Flash memory. The MX25L512E memory features a serial peripheral
interface and the protocol that uses three bus signals: clock input (SCLK), serial data
input (SI), and serial data output (SO). Serial access to the device is enabled by CS
input.
The following figure shows the SPI Flash interface circuit diagram.
MOSI 0
MISO 0
SCK0
SS0
VDD
VDD
U13
MX25L512E
CS
1
SO/SIO1
2
WP
3
G
N
D
4
SI/SIO0
5
SCLK
6
HOLD
7
V
C
C
8
E
P
9
C69
0.1 µF
R95
10K
R136
0
R134
0
R135
0
R133
0
R97
10K
GC10
GC9
GC7
GC8
Figure 9. SPI Flash interface circuit diagram
The following table describes the MX25L512E SPI Flash pin connection with the QSPI
controller of the MC56F80748.
MX25L512E pin/signal
MC56F80748 pin
Description
SI/SIO0
GPIOC10 (MOSI0)
Master-out Slave-in
SO/SIO1
GPIOC8 (MISO0)
Master-in slave-out
SCLK
GPIOC9 (SCK0)
Serial clock
CS
GPIOC7 (SS0)
Chip select
Table 13. MX25L512E SPI Flash pin connection
2.5 Resistor dividers
The three resistor dividers circuits are used on the MC56F80000-EVK board to test the
ADC block functions.
MC56F80000-EVKUM
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User manual
Rev. 1 — 14 December 2022
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