Daughter Card Description
MC1320x RF Daughter Card, Rev. 1.2
Freescale Semiconductor
9
NOTE
In the following sections, pin numbers not in parenthesis reference the
GB60 Development Board. Pin numbers in parenthesis reference the
M52235 Development Board.
5.1.0.1
SPI Connections
J101 pins 35 through 38 (J102 pin 17, 19, 21 and 23) provide the following four wire SPI interface:
•
MOSI
•
SPICLK
•
CE
•
MISO
The MC1320x always functions as a slave device. SPI operation is described in detail in the appropriate
MC1320x Data Sheet
and/or
MC1320x Reference Manual
.
NOTE
As it applies to the M52235 Development Board, the CE signal on (J102 Pin
23 and Pin 24) are hard wired to header J104. These pins control the
functionality of CE.
When Pin 2 and Pin 3 of J104 are shorted, CE is wired to (J102 Pin 24)
(PTE2/CE-AN7).
When Pin 1 and Pin 2 of J104 are shorted, CE is wired to (J102 Pin 23)
(PTE2/CE-QSPI_CS0).
5.1.0.2
Control Connections
•
J101 Pin 19 (J102 Pin 2) is the IRQ line from the MC1320x. Connection to the MCU depends on
how the MCU services interrupts.
•
J101 Pin 31 (J102 Pin 20), RXTXEN, allows the MCU to initiate transceiver functions.
•
J101 Pin 34 (J102 Pin 15), ATTN, allows the MCU to wake up the MC1320x from Doze or
Hibernate low power modes.
NOTE
RXTXEN and ATTN are also available at header J105 for manual control.
•
J101 Pin 24 provides the MC1320x CLKO to the MCU when a jumper is installed at J103.
•
J101 Pin 32 (J102 Pin13) interfaces with the MCU to provide a Reset to the MC1320x.
•
J101 Pin 5 and Pin 22 provide a wake up function to the MCU when a jumper is installed at J103.
•
J101 Pin 13 and Pin 14 (J102 Pin 9 and Pin 11) provide access to the MC1320x GPIO1 and GPIO2
ports.
