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UM10601
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© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
127 of 313
NXP Semiconductors
UM10601
Chapter 10: LPC800 State Configurable Timer (SCT)
10.6.18 SCT match registers 0 to 4 (REGMODEn bit = 0)
Match registers are compared to the counters to help create events. When the UNIFY bit
is 0, the L and H registers are independently compared to the L and H counters. When
UNIFY is 1, the L and H registers hold a 32-bit value that is compared to the unified
counter. A Match can only occur in a clock in which the counter is running (STOP and
HALT are both 0).
Match registers can be read at any time. Writing to a Match register while the associated
counter is running does not affect the Match register and results in a bus error. Match
events occur in the SCT clock in which the counter is (or would be) incremented to the
next value. When a Match event limits its counter as described in
, the
value in the Match register is the last value of the counter before it is cleared to zero (or
decremented if BIDIR is 1).
There is no “write-through” from Reload registers to Match registers. Before starting a
counter, software can write one value to the Match register used in the first cycle of the
counter and a different value to the corresponding Match Reload register used in the
second cycle.
10.6.19 SCT capture registers 0 to 4 (REGMODEn bit = 1)
These registers allow software to read the counter values at which the event selected by
the corresponding Capture Control registers occurred.
Table 124. SCT conflict flag register (CONFLAG, address 0x5000 40FC) bit description
Bit
Symbol
Description
Reset
value
3:0
NCFLAG
Bit n is one if a no-change conflict event occurred on output n
since reset or a 1 was last written to this bit (output 0 = bit 0,
output 1 = bit 1,..., output 3 = bit 3).
0
29:4
-
Reserved.
-
30
BUSERRL
The most recent bus error from this SCT involved writing CTR
L/Unified, STATE L/Unified, MATCH L/Unified, or the Output
register when the L/U counter was not halted. A word write to
certain L and H registers can be half successful and half
unsuccessful.
0
31
BUSERRH
The most recent bus error from this SCT involved writing CTR
H, STATE H, MATCH H, or the Output register when the H
counter was not halted.
0
Table 125. SCT match registers 0 to 4 (MATCH[0:4], address 0x5000 4100 (MATCH0) to
0x5000 4110 (MATCH4)) bit description (REGMODEn bit = 0)
Bit
Symbol
Description
Reset
value
15:0
VALMATCH_L When UNIFY = 0, read or write the 16-bit value to be compared
to the L counter. When UNIFY = 1, read or write the lower 16
bits of the 32-bit value to be compared to the unified counter.
0
31:16
VALMATCH_H When UNIFY = 0, read or write the 16-bit value to be compared
to the H counter. When UNIFY = 1, read or write the upper 16
bits of the 32-bit value to be compared to the unified counter.
0
