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UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
119 of 313
NXP Semiconductors
UM10601
Chapter 10: LPC800 State Configurable Timer (SCT)
10.6.3 SCT limit register
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
LIMIT_L and LIMIT_H. Both the L and H registers can be read or written individually or in
a single 32-bit read or write operation.
The bits in this register set which events act as counter limits. When a limit event occurs,
the counter is cleared to zero in unidirectional mode or changes the direction of count in
bidirectional mode. When the counter reaches all ones, this state is always treated as a
limit event, and the counter is cleared in unidirectional mode or, in bidirectional mode,
begins counting down on the next clock edge - even if no limit event as defined by the
SCT limit register has occurred.
3
CLRCTR_L -
Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0.
0
4
BIDIR_L
L or unified counter direction select
0
0
The counter counts up to its limit condition, then is cleared to zero.
1
The counter counts up to its limit, then counts down to a limit condition or to 0.
12:5
PRE_L
-
Specifies the factor by which the SCT clock is prescaled to produce the L or unified
counter clock. The counter clock is clocked at the rate of the SCT clock divided by
PRE_L+1.
Remark:
Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
0
15:13
-
Reserved
16
DOWN_H
-
This bit is 1 when the H counter is counting down. Hardware sets this bit when the
counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter is
counting down and a limit condition occurs or when the counter reaches 0.
0
17
STOP_H
-
When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related
to the counter can occur. If such an event matches the mask in the Start register, this
bit is cleared and counting resumes.
0
18
HALT_H
-
When this bit is 1, the H counter does not run and no events can occur. A reset sets
this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to
remove the halt condition and keep the SCT in the stop condition (not running), then
you can change the halt and stop condition with one single write to this register.
Remark:
Once set, this bit can only be cleared by software to restore counter
operation.
1
19
CLRCTR_H -
Writing a 1 to this bit clears the H counter. This bit always reads as 0.
0
20
BIDIR_H
Direction select
0
0
The H counter counts up to its limit condition, then is cleared to zero.
1
The H counter counts up to its limit, then counts down to a limit condition or to 0.
28:21
PRE_H
-
Specifies the factor by which the SCT clock is prescaled to produce the H counter
clock. The counter clock is clocked at the rate of the SCT clock divided by PRELH+1.
Remark:
Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing
the PRE value.
0
31:29
-
Reserved
Table 109. SCT control register (CTRL, address 0x5000 4004) bit description
Bit
Symbol
Value
Description
Reset
value
