UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
995 of 1269
NXP Semiconductors
UM10503
Chapter 38: LPC43xx UART1
38.6.10 UART1 Modem Status Register
The MSR is a read-only register that provides status information on the modem input
signals. MSR[3:0] is cleared on MSR read. Note that modem signals have no direct effect
on UART1 operation, they facilitate software implementation of modem signal operations.
38.6.11 UART1 Scratch Pad Register
The SCR has no effect on the UART1 operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the SCR has occurred.
38.6.12 UART1 Auto-baud Control Register
The UART1 Auto-baud Control Register (ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Table 860: UART1 Modem Status Register (MSR - address 0x4008 2018) bit description
Bit
Symbol
Value Description
Reset value
0
DCTS
Delta CTS.
Set upon state change of input CTS. Cleared on an MSR read.
0
0
No change detected on modem input, CTS.
1
State change detected on modem input, CTS.
1
DDSR
Delta DSR.
Set upon state change of input DSR. Cleared on an MSR read.
0
0
No change detected on modem input, DSR.
1
State change detected on modem input, DSR.
2
TERI
Trailing Edge RI.
Set upon low to high transition of input RI. Cleared on an MSR read.
0
0
No change detected on modem input, RI.
1
Low-to-high transition detected on RI.
3
DDCD
Delta DCD. Set upon state change of input DCD. Cleared on an MSR read. 0
0
No change detected on modem input, DCD.
1
State change detected on modem input, DCD.
4
CTS
-
Clear To Send State. Complement of input signal CTS. This bit is
connected to MCR[1] in modem loopback mode.
0
5
DSR
-
Data Set Ready State. Complement of input signal DSR. This bit is
connected to MCR[0] in modem loopback mode.
0
6
RI
-
Ring Indicator State. Complement of input RI. This bit is connected to
MCR[2] in modem loopback mode.
0
7
DCD
-
Data Carrier Detect State. Complement of input DCD. This bit is connected
to MCR[3] in modem loopback mode.
0
31:8
-
-
Reserved, the value read from a reserved bit is not defined.
NA
Table 861: UART1 Scratch Pad Register (SCR - address 0x4008 2014) bit description
Bit
Symbol Description
Reset value
7:0
Pad
Scratch pad. A readable, writable byte.
0x00
31:8
-
Reserved, the value read from a reserved bit is not defined.
NA