UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
978 of 1269
NXP Semiconductors
UM10503
Chapter 37: LPC43xx USART0_2_3
start bit is aligned with a clock edge (the clock may not have been running before). In this
case, the edge on the serial input data due to the start bit (logic 1 to 0) is used to
determine the start of the character.
The NOSTARTSTOPBITS bit of the Synchronous Mode Control register allows the user to
disable the transmission/ reception of the start and stop bits, improving the efficiency of
the USART. As a character is no longer identified by the start and stop bits, the serial clock
is used to determine the data bits. When the serial clock is running, all data that is
sampled is regarded as valid data.
In order to be able to identify the start of a character, the beginning of the character must
be aligned with the rising edge of the serial clock. For this reason, the FES bit of the
Synchronous Mode Control register is forced in hardware to ‘1’.
Directly after sampling the last bit, the character is stored in the receive FIFO.
Transmission
During synchronous slave mode, data can only be transmitted when the external serial
clock is running. Hence, when no start and stop bits are sent, transmission can only take
place when data is received from the master. When the start and stop bits are transmitted,
the external clock may only be detected after the first half of the received start bit
(sampling at the rising edge of the external serial clock). By using the edge created by the
received start bit (logic 1 to 0), it is made sure that the start bit of the character that is to be
transmitted by the slave is stable before this rising edge the external slave clock. In this
way it is ensured, that the master receives as many bits as it has transmitted.
When the first sample edge of the incoming serial clock samples a ‘1’ on the serial input
data (and start-stop bits are transmitted, thus the master has not initiated a transaction
yet), it is assumed that the master is running a continuous clock (instead of only running
the clock when sending data characters). The USART will not wait for a start bit from the
master, but will immediately start transmitting data when available. Note that in this
situation, the number of bits transmitted by the master and the number of bits transmitted
by the slave (received by the master) may not be aligned. It is assumed that a higher level
protocol ensures that complete characters are received when the master stops the clock.
Transmission of data during synchronous slave mode is most time-critical. First the
external serial input clock must be detected using edge detection logic. Then, data needs
to be shifted out and be stable before the sampling edge of the external serial clock.
Remark:
In this mode the u_clk period is allowed to be 4x the serial clock period.
37.7.5.2 Synchronous master mode
Synchronous master mode is enabled by setting the CSRC register bit to ‘1’. In this mode,
the external clock is generated internally by the baud-rate generation logic and is used to
clock the input and output serial data. The functionality of the baud-rate generation is
described in
. Auto-baud is not supported during synchronous mode. The
1x baud rate clock is used to shift out the serial output data and to sample the serial input
data.
Synchronous master mode behaves similar to the slave mode, except that the serial input
data is not registered at the interface but is clocked in the USART clock domain at the
sampling edge of the serial clock.
