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NXP Semiconductors

AN13125

IW416 Design Guide

•

There is a decoupling capacitor for each power pin and a bulk capacitor for each rail.

Place the decoupling capacitor as close as possible to the power pin, then place the

bulk capacitor.

shows an example where C9 is the decoupling capacitor for K5

pin. In this example, place C9 as close as possible to K5 pin, and place C58 close to

C9.

Figure 5. Decoupling capacitor and bulk capacitor placements

•

Do not place any analog power plane (trace) as ring and loop in the layout.

shows the correct top layer (left hand side of the figure) and the incorrect top layer

(right hand side). In the correct top layer, there is no loop on the AVDD18 net.

Figure 6. Power plane without loop

AN13125

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2021. All rights reserved.

Application note

Rev. 1 — 26 May 2021

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Содержание AN13125

Страница 1: ...ide Rev 1 26 May 2021 Application note Document information Information Content Keywords Power supply clock source reset host interface RF interface PCB layout PCB stackup Abstract Provides design guidelines for IW416 device ...

Страница 2: ...Design Guide Rev Date Description v 1 20210526 Initial version Revision history AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 2 33 ...

Страница 3: ...XP releases reference designs to provide examples on how to design a PCB using the device We strongly recommend follow these design guidelines closely Please contact your NXP representative to schedule a design review and discuss design options Note In the following sections the IW416 may be referred to as Wireless SoC AN13125 All information provided in this document is subject to legal disclaime...

Страница 4: ...face is used to lower the core voltage to reduce power consumption in sleep mode The power management interface uses two control signals DVSC1 and DVSC0 to dynamically adjust the voltage level from the power management IC PMIC Under normal operation the core voltage level is 1 05 V In sleep mode the core voltage is dropped to 0 8 V The following sections describe PMIC solutions from MPS NXP and Ma...

Страница 5: ...re used to control the core voltage level Table 2 shows the part numbers Figure 1 Power supply by MPS PMICs Manufacturer Part number MPS BUCK MP2162AGQH C867 Z MPS BUCK MP2182GTL C867 Z MPS BUCK MP8904DD C867 LF Z Table 2 MPS PMICs part numbers AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 5 33 ...

Страница 6: ...88PG823 QFN Manufacturer Part number Marvell QFN package option 88PG823 xx NPD2C000 Marvell WLCSP package option 88PG823 xx CBK2 T NXP QFN package option PM823HN A0CHP NXP WLCSP package option PM823UK A0CZ Table 3 Marvell and NXP PMICs part numbers 2 4 Power up sequence requirements All the power rails must meet correct power up sequence Refer to IW416 data sheet AN13125 All information provided i...

Страница 7: ...d vias as close as possible to the decoupling capacitors as shown in Figure 3 Figure 3 Power vias and ground vias Ensure each power pin has its own decoupling capacitor Place the decoupling capacitors as close as possible to the power pin The power from source to the power pin should go through the decoupling network before connecting to the power pin As shown in Figure 4 Figure 4 Example of power...

Страница 8: ... as possible to K5 pin and place C58 close to C9 Figure 5 Decoupling capacitor and bulk capacitor placements Do not place any analog power plane trace as ring and loop in the layout Figure 6 shows the correct top layer left hand side of the figure and the incorrect top layer right hand side In the correct top layer there is no loop on the AVDD18 net Figure 6 Power plane without loop AN13125 All in...

Страница 9: ...he internal capacitor in the Wireless SoC is used to tune the crystal frequency External loading capacitors are typically not needed Figure 7 Typical crystal circuit PCB layout guidelines for the crystal Refer to the following guidelines for the crystal Place the crystal close to the device and keep it as far away as possible from the RF side of the device and high frequency signal traces such as ...

Страница 10: ...n the second layer Place the ground guard with ground stitching vias around the XTAL_IN and XTAL_OUT traces as shown in Figure 8 To minimize the reference clock signals cut out all internal metal planes under the crystal and keep the last ground plane as the reference plane AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Applicatio...

Страница 11: ...ator Follow the external oscillator vendor s recommendations for the layout Place the oscillator as far as possible from the Wireless SoC RF side Keep the clock trace as short as possible Ground the guard trace with the ground via around the clock trace 3 3 Sleep clock An optional external sleep clock may be used to further reduce the power consumption in sleep mode Note the following The external...

Страница 12: ...n usage 4 2 Reset strap configuration It is critical to set the reset configuration pins correctly at reset to ensure the proper configuration for the Wireless SoC Refer to IW416 data sheet for details on the configuration pins and host configuration options 4 3 PCB layout guidelines Do not route PDn signal next to a large switching signal or on the edge of the PCB to avoid EMI affecting the reset...

Страница 13: ... MHz clock speed The required pull up for SDIO interface on SD_CMD and SD_D 3 0 signals should be provided by the host The pull up value is between 10 kΩ to 100 kΩ according to SDIO v3 0 specifications Series damping resistors may be needed to help with signal integrity issues When extending the SDIO signals through ribbon cable series resistors of 75 Ω are recommended to reduce the undershoot ove...

Страница 14: ...und plane along with SDIO signals with stitch vias as shown in Figure 12 Figure 12 Place ground between SDIO signals with ground stitch vias Avoid routing power supply traces under or above SDIO signal traces If SDIO signal traces are routed on one of the inner layers then make sure to shield them by having solid ground above and below SDIO traces The bend trace routing should be smooth with a lar...

Страница 15: ...Figure 14 shows a typical application circuit for the UART interface Figure 14 UART host interface connections AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 15 33 ...

Страница 16: ... antenna is for Bluetooth In a single antenna application the antenna is shared between Wi Fi and Bluetooth Figure 15 shows the typical front end topology for a two antenna application Use discrete low pass filters LPF to ensure the rejection of out of band emissions LPF components also act as impedance matching circuits between the wireless SoC pin and the diplexer part on the PCB For maximum pow...

Страница 17: ...ng recommendations To reduce the impact of mutual interference provide at least 30 dB isolation between the two antennas Keep the antenna gain to a minimum outside the 2 4 and 5 GHz bands In applications where the antenna isolation is limited the transmit power level for the Bluetooth radio may need to be reduced The transmit power level depends on various system design factors such as antenna gai...

Страница 18: ...put output impedance needs to match 50 Ω Refer to Figure 16 for the filter circuit on Wi Fi 2 4 GHz path Figure 18 RF Front end for single antenna application Table 5 lists the recommended RF front end components RF component Manufacturer Part number Diplexer TDK DPX166000DT 8093A1 SPDT switch SKYWORKS SKY13323 378LF Discrete LPF on Wi Fi 2 4 GHz path L 2 1 nH 0 1 nH 0201 C 0 6 pF 0201 Discrete LP...

Страница 19: ...ure 19 shows a typical front end topology for dual antenna applications Figure 19 RF front end with dual antenna applications Use discrete low pass filters LPF to ensure the rejection of out of band emissions LPF components also act as impedance matching circuits between the wireless SoC pin and the diplexer part on the PCB For maximum power transfer in RF the input output impedance needs to match...

Страница 20: ...ponent Manufacturer Part number Diplexer TDK DPX166000DT 8193A1 SPDT switch SKYWORKS SKY13323 378LF Discrete LPF on Wi Fi 2 4 GHz path L 2 1 nH 0 1 nH 0201 C 0 6 pF 0201 Discrete LPF on Bluetooth path C 1 6 pF 0201 L 3 3 nH 0 1 nH 0201 C 1 6 pF 0201 Table 6 Recommended RF front end components AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights ...

Страница 21: ...ons LPF components also act as impedance matching circuits between the wireless SoC pin and the diplexer part on the PCB For maximum power transfer in RF the input output impedance needs to match 50 Ω Refer to Figure 16 for the filter circuit on Wi Fi 2 4 GHz path Keep the antenna gain to a minimum outside the 2 4 GHz and 5 GHz bands An RF shield is recommended to minimize radiated emissions and a...

Страница 22: ...our and RF micro strip to minimize the impact on the micro strip impedance Maintain this gap around any RF signal via as shown in Figure 22 Figure 22 3X H clearance between the ground pour and RF trace Keep the RF trace lengths as short as possible The bend trace routing should be smooth with a large radius rather than of 90 degree with a sharp edge AN13125 All information provided in this documen...

Страница 23: ...n in Figure 24 Figure 24 Ground pour along with RF trace end with a ground via Keep the RF control signal traces as far away as possible from the RF traces Follow the manufacturer s recommendations for RF front end parts that require matching networks RF ground via along the RF shield must be less than 100 mil interval Ground via must be close to the matching capacitor ground pin AN13125 All infor...

Страница 24: ... avoid discontinuity and high insertion loss especially at 5 GHz band An example is shown in Figure 25 Figure 25 Taper line for RF trace to connector AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 24 33 ...

Страница 25: ...bout 20 mil Add ground vias close to the diplexer ground pins for a good return path If an ESD protection inductor is required place the inductor close to the RF connector or close to the ESD sensitive front end component An RF shield is recommended to minimize radiated emissions and any RF interference Avoid clock signal routes system clock SDIO_CLK SLP_CLK crossing the power supply traces or vic...

Страница 26: ...relief as shown in Figure 27 Make sure the GND EPAD has a good number of thermal vias for the thermal path to be effective Figure 27 Ground EPAD for QFN package AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 26 33 ...

Страница 27: ...ductor keep out areas are highlighted in Figure 28 Figure 28 On chip inductor area under WLCSP package For additional details refer to DXF drawing layer included in Wireless SoC WLCSP reference design PCB layout file on NXP website AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 27 33 ...

Страница 28: ...V supply rail VIO_SD Connect to 1 8 V supply rail VIO_RF Connect to 1 8 V or 3 3 V supply rail Table 7 Unused pins Table 8 shows the PCB connection for unused interfaces Interface PCB connection when not used SDIO interface Keep floating No connect UART interface Keep floating No connect PCM interface Keep floating No connect WCI 2 interface Keep floating No connect Table 8 Unused interfaces 7 2 G...

Страница 29: ...XP reference design PCB typically consists of six layers with FR 4 material and blind buried vias Figure 29 shows the typical 6 layer PCB stack up for WLCSP package Figure 29 PCB stackup for WLCSP package AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Rev 1 26 May 2021 29 33 ...

Страница 30: ...FN package Figure 30 Six layer PCB stackup for QFN package Figure 31 shows the typical four layer PCB stackup for QFN package Figure 31 Four layer PCB stackup for QFN package In general RF routing is on the top layer with RF trace reference ground is on the layer 2 AN13125 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserved Application note Re...

Страница 31: ...ird party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described he...

Страница 32: ...ng 14 Fig 14 UART host interface connections 15 Fig 15 RF front end for two antenna application 16 Fig 16 Discrete LPF on Wi Fi 2 4GHz RF path 17 Fig 17 Discrete LPF on Bluetooth RF path 17 Fig 18 RF Front end for single antenna application 18 Fig 19 RF front end with dual antenna applications 19 Fig 20 Circuit diagram for SPDT switch on Wi Fi 5 GHz path 20 Fig 21 RF front end for single antenna a...

Страница 33: ... interface 13 5 1 SDIO interface 13 5 2 UART interface 15 6 RF interface 16 6 1 RF front end for QFN package 16 6 2 RF front end for WLCSP package 19 6 3 PCB layout guidelines 22 7 Miscellaneous 28 7 1 Unused interfaces and pins 28 7 2 GPIOs 28 7 3 PCB stackup 29 8 Legal information 31 Please be aware that important notices concerning this document and the product s described herein have been incl...

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