NXP Semiconductors AN10365, Примечание к применению

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AN10365_3 © NXP B.V. 2008. All rights reserved.
Application note Rev. 03 — 22 April 2008 6 of 24
NXP Semiconductors
AN10365
Surface mount reflow soldering description
All footprints within a package family (in this example all SSOP packages) use the same
generic footprint drawing, regardless of the actual number of package terminals. In this
example, it is not accidental that the generic footprint drawing shows 18 terminals,
whereas the SSOP20 package has 20 terminals. The table on the PCB footprint, below
the drawing, shows the actual dimensions for the specific package outline (with 20
terminals), while the generic drawing is used to illustrate the dimensions. The real
package outline (with the correct number of terminals) can be found under ‘Package
information’ on the ‘Product information’ page of the NXP Semiconductors web site at the
URL given in “Contact information” at the bottom of page 2.
The soldering process is carried out under a set of process parameters that includes
accuracies in the process, and IC package, board, and stencil tolerances. The footprint
design is directly related to these aspects of the soldering process; the calculation of
these dimensions is based on process parameters that are compliant with modern
machines and a state-of-the-art process.
A solder resist layer (also known as a solder mask layer) is usually applied to the board, to
isolate the solder lands and tracks. If this solder resist extends onto the Cu, the remaining
solderable area is solder resist defined. This is sometimes referred to as Solder Mask
Defined (SMD).
Figure 3 shows solder resist defined pads; yellow is Cu and dark green is
solder resist. The Cu underneath the solder resist is shown in a lighter shade of green.
The alternative situation is that the solder resist layer starts outside of the Cu. In that case,
the solder lands are Cu defined. This is sometimes referred to as Non Solder Mask
Defined (NSMD). A Cu defined layout is shown in
Figure 4 (white is the bare board).
A layout may also be partially solder resist defined and partially Cu defined.
Fig 3. Solder resist defined solder lands
Fig 4. Cu defined solder lands
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