NXP Semiconductors A3M39SL039, Техническое описание

Страница: 22 / 33

Design considerations
A3M39SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, March 2022
Data Sheet: Technical Data 22 / 33
9.3.2 I 2 C bus electrical characteristics
Table 20. I 2 C SCLK and SDA
Symbol Parameter Conditions Min Max Unit
V
IL
LOW-level input voltage — — 0.3*V
DD1
V
V
IH
HIGH-level input voltage — 0.7*V
DD1
— V
V
hys
Hysteresis of Schmitt trigger inputs — 0.05*V
DD1
— V
V
OL
LOW-level output voltage
(Open-drain/open-collector) at
2 mA sink current V
DD1
= < 2 V
0 0.2*V
DD1
V
V
OH
HIGH-level output voltage (Open-drain/open-collector) 0.7*V
DD1
V
DD1
V
I
OL
LOW-level output current
V
OL
= 0.4 V 3 — mA
V
OL
= 0.6 V 6 — mA
I
iL
Input leakage current at the pin
V
DD
= 1.8, Pin voltage = 1.8 V,
0.1 V
DD
< VI < 0.9 V
DD1
–10 10 µA
C
i
Capacitance for each I/O pin — — 10 pF
t
SP
Pulse width of spikes that must be
suppressed by the input filter
— 0 50 ns
t
of
Output fall time from V
IH(min)
to V
IL(max)
Pullup res = 250 ohm and max
allowed load capacitance C
b
— 250 ns
C
b
Capacitive load for each bus line 2 — — 400 pF
1. V
DD
in this table refers to 1.8 V provided by the Leader.
2. The maximum t
f
for the SDA and SCLK bus lines is specified at 300 ns. This allows series protection resistors to be
connected in between the SDA and the SCLK pins and the SCLK bus lines without exceeding the maximum specified t
f
.
10 Design considerations
10.1 Power on sequence
The initial power on sequence will take approximately 200 µs to complete the OTP memory fetching process. Therefore, it is
suggested to wait at least 200 µs before issuing the SPI or I 2 C read and write processes. The normal SPI or I 2 C read and write
processes should follow the sequence illustrated in Figure 1 1 , “Power on sequence timing diagram.”
Figure 11. Power on sequence timing diagram